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resources:eval:ad9650-105ebz_ad9268-125ebz_ad9269-80ebz_ad9648-125ebz [22 Nov 2021 07:56] – [Design and Integration Files] Meriam Yuson-Aguilaresources:eval:ad9650-105ebz_ad9268-125ebz_ad9269-80ebz_ad9648-125ebz [03 Dec 2021 02:38] – [Troubleshooting Tips] Meriam Yuson-Aguila
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 ===== Typical Measurement Setup ===== ===== Typical Measurement Setup =====
-{{:resources:eval:ad9230_set-up.jpg?600|}}+{{ :resources:eval:ad9268_typical_setup.jpg?600 |}}
 <WRAP centeralign> <WRAP centeralign>
 //Figure 1. Evaluation Board Connection—[[adi>AD9650|AD9650-105EBZ]], [[adi>AD9268|AD9268-125EBZ]], [[adi>AD9258|AD9258-125EBZ]], [[adi>AD9251|AD9251-80EBZ]], [[adi>AD9231|AD9231-80EBZ]], [[adi>AD9204|AD9204-80EBZ]], [[adi>AD9269|AD9269-80EBZ]], [[adi>AD9648|AD9648-125EBZ]], [[adi>AD9628|AD9628-125EBZ]] or [[adi>AD9608|AD9608-125EBZ]] (on Left) and [[adi>hsadcevalboard|HSC-ADC-EVALCZ]] (on Right)// //Figure 1. Evaluation Board Connection—[[adi>AD9650|AD9650-105EBZ]], [[adi>AD9268|AD9268-125EBZ]], [[adi>AD9258|AD9258-125EBZ]], [[adi>AD9251|AD9251-80EBZ]], [[adi>AD9231|AD9231-80EBZ]], [[adi>AD9204|AD9204-80EBZ]], [[adi>AD9269|AD9269-80EBZ]], [[adi>AD9648|AD9648-125EBZ]], [[adi>AD9628|AD9628-125EBZ]] or [[adi>AD9608|AD9608-125EBZ]] (on Left) and [[adi>hsadcevalboard|HSC-ADC-EVALCZ]] (on Right)//
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   - Adjust the amplitude of the input signal so that the fundamental is at -1.0 dBFS. Examine the **Fund Power** reading in the left panel of the **VisualAnalog Graph - AD9268 Average FFT** window (see Figure 14) to verify this.{{ :resources:eval:ad9268_graph_window_of_va.jpg?400 |}}<WRAP centeralign>//Figure 14. Graph Window of VisualAnalog //</WRAP>   - Adjust the amplitude of the input signal so that the fundamental is at -1.0 dBFS. Examine the **Fund Power** reading in the left panel of the **VisualAnalog Graph - AD9268 Average FFT** window (see Figure 14) to verify this.{{ :resources:eval:ad9268_graph_window_of_va.jpg?400 |}}<WRAP centeralign>//Figure 14. Graph Window of VisualAnalog //</WRAP>
   - Repeat this procedure for Channel B.   - Repeat this procedure for Channel B.
-  - Click the disk icon within the **Graph** window to save the performance plot data as .csv formatted file. See Figure 15 for an example.{{ :resources:eval:ad9268_typ_fft.jpg?400 |}}<WRAP centeralign>//Figure 14. Graph Window of VisualAnalog //</WRAP>    +  - Click the disk icon within the **Graph** window to save the performance plot data as .csv formatted file. See Figure 15 for AD9268 example. Please refer to the respective data sheet of the product of interest for its typical FFT performance.{{ :resources:eval:ad9268_typ_fft.jpg?400 |}}<WRAP centeralign>// Figure 15. Typical FFT, AD9268//</WRAP> 
-  - On the VA canvas, examine SNRFS and SFDR to insure you see the following results for the Evaluation Board specifications: +  
-For Input Frequency fIN = 70 MHz, +
-SNRFS is equal to or greater than 77.2dBFS and typically equal to 78dBFS. +
-SFDR is equal to or greater than 85dBFS and typically equal to 88dBFS. +
-See Table 3 for desired results. +
-== Table 3. == +
-^Family Name         ^Unit       ^Requirement                    | +
-|Fund Power*          |dBFS       |~-1|              +
-|SNRFS               |dBFS       |>76| +
-|SFDR                |dBC        |>83| +
-*Note: After adjusting Ain level on Signal Generator, on FFT Screen of Visual Analog     +
-                                    +
 ===== Troubleshooting Tips ===== ===== Troubleshooting Tips =====
 If the FFT plot appears abnormal, do the following: If the FFT plot appears abnormal, do the following:
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   - Make sure that all power and USB connections are secure.   - Make sure that all power and USB connections are secure.
   - Probe the DCOA signal at RN801 (Pin 2) on the evaluation board and confirm that a clock signal is present at the ADC sampling rate.   - Probe the DCOA signal at RN801 (Pin 2) on the evaluation board and confirm that a clock signal is present at the ADC sampling rate.
 +
 +For AD9648 Family, it is worthwhile to perform Digital Reset if there is unexpected behavior to ensure that the ADC is initialized properly.
 +  * SPI_Write (0x08, 0x03); #digital reset
 +  * SPI_Write (0x08, 0x00); #normal operation
  
resources/eval/ad9650-105ebz_ad9268-125ebz_ad9269-80ebz_ad9648-125ebz.txt · Last modified: 08 Jan 2024 02:07 by Janadrian Alipio

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