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This user guide describes the evaluation boards, AD9650-105EBZ, AD9268-125EBZ, AD9258-125EBZ, AD9251-80EBZ, AD9231-80EBZ, AD9204-80EBZ, AD9269-80EBZ, AD9648-125EBZ, AD9628-125EBZ and AD9608-125EBZ that are used to evaluate the following Analog Devices, Inc., products: AD9650, AD9268, AD9258, AD9251, AD9231, AD9204, AD9269, AD9648, AD9628 and AD9608. These evaluation boards provide all of the support circuitry required to operate these parts in their various modes and configurations. The application software used to interface with the devices is also described.
The AD9650, AD9268, AD9258, AD9251, AD9231, AD9204, AD9269, AD9648, AD9628 and AD9608 data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at www.analog.com/hsadcevalboard. For additional information or questions, send an email to firstname.lastname@example.org.
This section provides quick start procedures for using the AD9650-105EBZ, AD9268-125EBZ, AD9258-125EBZ, AD9251-80EBZ, AD9231-80EBZ, AD9204-80EBZ, AD9269-80EBZ, AD9648-125EBZ, AD9628-125EBZ or AD9608-125EBZ board. Both the default and optional settings are described.
Before using the software for testing, configure the evaluation board as follows:
The evaluation board provides all of the support circuitry required to operate the AD9650, AD9268, AD9258, AD9251, AD9231, AD9204, AD9269, AD9648, AD9628 and AD9608 in their various modes and configurations. Figure 1 shows the typical bench characterization setup used to evaluate AC performance. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the signal chain. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is necessary to achieve the specified noise performance.
The evaluation board covers multiple families of ADCs and is populated slightly differently between the families. Table 1 shows the four main families and the ADCs that fall within each family. When a reference is made to the AD9269, for example, this applies to all the ADCs within that family, that is, the AD9251, the AD9231, and the AD9204, and the AD9269.
|Family Name||ADCs within Each Family|
|AD9269||AD9251, AD9231, AD9204, AD9269|
|AD9648||AD9648, AD9628, AD9608|
See the Getting Started section to get started, and Design and Integration Files sections for the complete schematics and layout diagrams. These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters.
This evaluation board comes with a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to a 100 V ac to 240 V ac, 47 Hz to 63 Hz wall outlet. The output from the supply is provided through a 2.1 mm inner diameter jack that connects to the printed circuit board (PCB) at P101. The 6 V supply is fused and conditioned on the PCB before connecting to the low dropout linear regulators (default configuration) that supply the proper bias to each of the various sections on the board.
The evaluation board can be powered in a nondefault condition using external bench power supplies. To do this, E101, E102, E114, E103, E105 and E107 ferrite beads can be removed to disconnect the outputs from the on-board LDOs. This enables the user to bias each section of the board individually. Use P102 and P103 to connect a different supply for each section. A 1.8 V supply is needed with 1A current capability for DUT_AVDD and DRVDD; however, it is recommended that separate supplies be used for both analog and digital domains. An additional supply is also required to supply 1.8 V for digital support circuitry on the board, DVDD. This should also have a 1 A current capability and can be combined with DRVDD with little or no degradation in performance. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply is needed in addition to the other supplies. This 3.3 V supply, or 3V_CLK, should have a 1 A current capability.
Two additional supplies, 5V_AMPVDD and 3V_AMPVDD, are used to bias the optional input path amplifiers and optional VREF buffer. If used, these supplies should each have 1 A current capability.
A second optional power supply configuration allows replacing the LDOs that supply the AVDD and DRVDD rails of the ADC with the ADP2114 step-down dc-to-dc regulator. Using this switching controller in place of the LDO regulators to power the AVDD and DRVDD supplies of the ADC allows customers to evaluate the performance of the ADC when powered by a more efficient regulator.
When connecting the ADC clock and analog source, use clean signal generators with low phase noise, such as the Rohde & Schwarz SMA, or HP 8644B signal generators or an equivalent. Use a 1 m shielded, RG-58, 50 Ω coaxial cable for connecting to the evaluation board. Enter the desired frequency and amplitude in the signal generators (see the Specifications section in the data sheet of the respective part). When connecting the analog input source, use of a multipole, narrow-band band-pass filter with 50 Ω terminations is recommended. Analog Devices, Inc., uses band-pass filters from TTE, Allen Avionics and K & L Microwave, Inc. Connect the filters directly to the evaluation board.
If an external clock source is used, it should also be supplied with a clean signal generator as previously specified. Analog Devices evaluation boards typically can accept ~2.8 V p-p or 13 dBm sine wave input for the clock.
The default setup uses the Analog Devices high speed converter evaluation platform (HSC-ADC-EVALCZ) for data capture. The CMOS output signals from Channel A and Channel B are buffered through U801 and U802 and are routed through P903 and P902, respectively, to the FPGA on the data capture board. For more information on the data capture board and its optional settings, visit www.analog.com/hsadcevalboard.
Connect the switching power supply that is supplied in the evaluation kit between a rated 100V ac to 240V ac wall outlet (at 47 Hz to 63 Hz) and P101.
Figure 2. Default Analog Input Configuration of the AD9650 Family
Figure 3. Default Analog Input Configuration of the AD9268 Family
Figure 4. Default Analog Input Configuration of the AD9269 Family
The default input network, as configured on the AD9650 evaluation board, is shown in Figure 2.
For the AD9268 family, the default analog input configuration supports analog input frequencies of up to ~250 MHz (see Figure 3). The input network is optimized to support a wide frequency band. See the AD9258 and AD9268 data sheets for additional information on the recommended networks for different input frequency ranges.
For the AD9269 family, the default analog input configuration supports analog input frequencies of up to ~150 MHz (see Figure 4). The nominal input drive level is 10dBm to achieve 2 V p-p full scale into 50 Ω. At higher frequencies, slightly higher input drive levels are required due to losses in the front-end network.
Optionally, the Channel A input on the board can be configured to use the AD8375 digitally variable gain amplifier (DVGA). The AD8375 component is included on the evaluation board at U401. However, the path into and out of the AD8375 can be configured in many different ways depending on the application; therefore, the parts in the input and output path are left unpopulated. Users should see the AD8375 data sheet for additional information on the part and for configuring the inputs and outputs. The AD8375 by default is held in power-down mode but can be enabled by adding a jumper on J403.
The Channel B input is also set up with an optional input path through the ADL5562 ultralow distortion RF/IF differential amplifier. Similar to Channel A, the amplifier is included on the board at U501; however, the input-/output-related components are not included. Users should see the ADL5562 data sheet for additional information on this part and for configuring the inputs and outputs. The ADL5562 is also normally held in power-down mode and can be enabled by adding a jumper on J503. The ADL5562 on the Channel B input can also be substituted with ADA4937 or the ADA4938 to allow evaluation of these parts with the ADC.
The default VREF configuration is to connect the SENSE pin to AGND for internal VREF operation. This is done by connecting Pin 4 and Pin 6 on Header J201. Table 2 summarizes the internal VREF voltage for the different families of ADCs.
|Family Name||Internal VREF (V)||Full-Scale Range (V p-p)|
The AD9650 and AD9269 families operate with a fixed reference. For the AD9268 family, the reference voltage can be changed to 0.5 V for a 1.0 V p-p full-scale range by moving the SENSE pin jumper connection on J201 from Pin 4 through Pin 6 to Pin 3 through Pin 4 (this connects the SENSE pin to the VREF pin).
To use the programmable reference mode for the AD9268 family, a resistor divider can be set up by installing R204 and R205. The jumper on J201 should be removed for this mode of operation. See the data sheet of the specific part for the additional information on using the programmable reference mode.
A separate unpopulated external reference option using the AD1580 reference and the AD822 amplifier is also included on the evaluation board. To enable the external reference populate CR201, U202, R202, R201, C201 and C202 with the values shown in the Evaluation Board schematics. The J201 jumper should be placed between Pin 4 and Pin 2 to set the reference input to the external reference mode.
RBIAS has a default setting of 10 kΩ (R206) to ground and is used to set the ADC core bias current. Note that using a resistor value other than a 10 kΩ, 1% resistor for RBIAS may degrade the performance of the device.
The default clock input circuit on the AD9269 evaluation board family uses a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T601) that adds a low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped by CR601 before entering the ADC clock inputs.
The AD9269 evaluation board family is by default set up to be clocked through the transformer-coupled input network from the crystal oscillator, Y601. This oscillator is a low phase noise oscillator from Valpey Fisher (VFAC3-BHL-40MHz/ VFAC3-BHL-65MHz/VFAC3-BHL-80MHz). If a different clock source is desired, remove J605 to disable the oscillator from running and connect the external clock source to the SMA connector, J602 (labeled ENCODE+).
The default clock input circuitry on the AD9650 and AD9268 family evaluation boards uses a similar circuit to the AD9269 family but uses a higher bandwidth 1:1 impedance ratio balun (T602) that adds a low amount of jitter to the clock path. The clock input is again 50Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The balun converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs.
The board is set by default to use an external clock generator. An external clock source capable of driving a 50 Ω terminated input should be connected to J602. This family is shipped from Valpey Fisher with a low phase noise oscillator installed. The oscillator frequency is set to match the rated speed of the part: 125 MHz, 105 MHz, or 80 MHz for the AD9268 family and 105 MHz, 80 MHz, 65 MHz, or 25 MHz, for the AD9650 family. To enable the oscillator, install J605, and to connect it into the clock path, add a 0 Ω resistor at C610. R602 should also be removed to remove the 50 Ω termination from the output of the oscillator.
A differential LVPECL clock driver output can also be used to clock the ADC input using to AD9517 (U701). To place the AD9517 into the clock path, populate R607 and R608 with 0 Ω resistors and remove R609 and R610 to disconnect the default clock path inputs. In addition, populate R731 and R732 with 0 Ω resistors and remove R611 and R612 to disconnect the default clock path outputs and insert the AD9517 LVPECL Output 3. The AD9517 must be configured through SPI controller software to set up the PLL and other operation modes. Consult the AD9517 data sheet for more information about these and other options.
To enable the power-down feature, add a shorting jumper across J205 at Pin 1 and Pin 2 to connect the PDWN pin to DRVDD.
To disable the outputs using the /OE pin, add a shorting jumper across J205 at Pin 3 and Pin 4 to connect the /OE pin to DRVDD.
For users who want to operate the DUT without using SPI, remove the shorting jumpers on J302. This disconnects the /CS, SCLK/DFS and SDIO/DCS pins from the SPI control bus, allowing the DUT to operate in non-SPI mode. In this mode, the SCLK/DFS and SDIO/DCS pins take on their alternate functions to select data format and enable/disable the DCS. With the jumpers removed, DCS is disabled; to enable DCS, add a shorting jumper on J302 between Pin 2 to Pin 3. With the jumper removed, the data format is set to offset binary. To set the data format to twos complement, a jumper should be added on J302 between Pin 5 and Pin 6.
Optionally, the ADC on the board can be configured to use the ADP2114 dual switching power supply to provide power to the DRVDD and AVDD rails of the ADC. To configure the board to operate from the ADP2114, the following changes must be incorporated. See Design and Integration Files for specific recommendations for part values):
Making these changes enables the switching converter to power the ADC. Using the switching converters as the ADC power source is more efficient than using the default LDOs.
After configuring the board, set up the ADC data capture using the following steps:
Figure 5. VisualAnalog, New Canvas Window
Figure 7. VisualAnalog Window Toolbar, Collapsed Display
Figure 8. VisualAnalog, Main Window Expanded Display
After the ADC data capture board setup is complete, set up the SPI controller software using the following procedure:
Figure 9. SPI Controller, CHIP ID(1) Box
Figure 11. SPI Controller, ADCBase0 Page
Figure 12. SPI Controller, Example ADC A Page
The next step is to adjust the amplitude of the input signal for each channel as follows:
For Input Frequency fIN = 70 MHz, SNRFS is equal to or greater than 77.2dBFS and typically equal to 78dBFS. SFDR is equal to or greater than 85dBFS and typically equal to 88dBFS. See Table 3 for desired results.
*Note: After adjusting Ain level on Signal Generator, on FFT Screen of Visual Analog
If the FFT plot appears abnormal, do the following:
If the FFT appears normal but the performance is poor, check the following:
If the FFT window remains blank after Run is clicked, do the following:
If VisualAnalog indicates that the FIFO Capture timed out, do the following: