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university:courses:electronics:electronics-lab-scr [24 Jul 2017 16:10] – change amplitude value to peak-peak Antoniu Miclausuniversity:courses:electronics:electronics-lab-scr [27 May 2022 21:00] (current) – [LATCH-UP] Doug Mercer
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-======Activity: Silicon Controlled Rectifiers (SCR)======+======Activity: Silicon Controlled Rectifiers (SCR) - ADALM2000======
  
 =====Objective:===== =====Objective:=====
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 =====Hardware Setup:===== =====Hardware Setup:=====
  
-AWG1 should be configured as a sine wave with an amplitude of 10 V, zero offset and a frequency of 100  +AWG1 should be configured as a sine wave with an amplitude of 10 V peak-to-peak, zero offset and a frequency of 100  
-Hz. AWG2 should be configured as a square wave with an amplitude of 800 mV, 400 mV offset, a frequency  +Hz. AWG2 should be configured as a square wave with an amplitude of 800 mV peak-to-peak, 400 mV offset, a frequency  
-of 100 Hz and a duty cycle (symmetry) of 10%. 10% is the narrowest pulse width allowed by the Scopy  +of 100 Hz. Be sure to run the two AWG channels synchronously. 
-software. Be sure to run the two AWG channels synchronously.+{{ :university:courses:electronics:ascr_bb.png? |}} 
 + 
 +<WRAP centeralign> Figure 3 Breadboard connections of Circuit to emulate an SCR </WRAP>
  
 =====Procedure:===== =====Procedure:=====
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 Trigger the scope on channel 1. While observing the input sine wave on scope channel 1 and the voltage  Trigger the scope on channel 1. While observing the input sine wave on scope channel 1 and the voltage 
 across R<sub>L</sub> on scope channel 2, adjust the phase of AWG2 in steps from 180º to 360º. Depending  across R<sub>L</sub> on scope channel 2, adjust the phase of AWG2 in steps from 180º to 360º. Depending 
-on the phase setting of AWG2 you should see something that looks similar to figure 3. You will notice +on the phase setting of AWG2 you should see something that looks similar to the figures below. You will notice 
 that the voltage across R<sub>L</sub> is zero, SCR in OFF state, until the trigger pulse from AWG2  that the voltage across R<sub>L</sub> is zero, SCR in OFF state, until the trigger pulse from AWG2 
 occurs and the SCR remains in the ON state until the input sine wave voltage crosses zero. occurs and the SCR remains in the ON state until the input sine wave voltage crosses zero.
- 
 {{ :university:courses:electronics:ascr_f3.png?500 |}} {{ :university:courses:electronics:ascr_f3.png?500 |}}
  
-<WRAP centeralign> Figure 3 Example waveforms </WRAP>+<WRAP centeralign> Figure 4 Example waveforms </WRAP> 
 + 
 + 
 +{{ :university:courses:electronics:ascr_f3a.png? |}} 
 + 
 +<WRAP centeralign> Figure 5 Example Scopy waveforms </WRAP>
  
 Measure and report the voltage drop across the SCR when it is in the ON state and conducting current. How does this voltage compare to a conventional PN junction diode? Measure and report the voltage drop across the SCR when it is in the ON state and conducting current. How does this voltage compare to a conventional PN junction diode?
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 Latch-up is a potentially destructive situation in which a parasitic SCR is triggered, shorting the  Latch-up is a potentially destructive situation in which a parasitic SCR is triggered, shorting the 
-positive and negative supplies together. If current flow is not limited, electrical overstress will +positive and negative supplies together. If current flow is not limited, electrical over-stress will 
 occur. The classic case of latch-up occurs in CMOS output devices, in which the driver transistors and  occur. The classic case of latch-up occurs in CMOS output devices, in which the driver transistors and 
 wells form a four layer PNPN SCR structure when one of the two parasitic base-emitter junctions is  wells form a four layer PNPN SCR structure when one of the two parasitic base-emitter junctions is 
-momentarily forward biased during an overvoltage upset event. The SCR turns on and essentially causes a +momentarily forward biased during an over-voltage upset event. The SCR turns on and essentially causes a 
 short between the V<sub>DD</sub> power supply and ground. short between the V<sub>DD</sub> power supply and ground.
  
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 {{ :university:courses:electronics:ascr_f4.png?650 |}} {{ :university:courses:electronics:ascr_f4.png?650 |}}
  
-<WRAP centeralign> Figure 4 Cross-section of PMOS and NMOS devices, with parasitic transistors Q<sub>1</sub> and Q<sub>2</sub> </WRAP>+<WRAP centeralign> Figure 6 Cross-section of PMOS and NMOS devices, with parasitic transistors Q<sub>1</sub> and Q<sub>2</sub> </WRAP>
  
-Proper design methods to reduce the possiblility of SCR formation include increasing the spacing between  +Proper design methods to reduce the possibility of SCR formation include increasing the spacing between  
-NMOS and PMOS devices and interposing highly doped regions bweteen and around Nwells and Pwells. Both of +NMOS and PMOS devices and interposing highly doped regions between and around Nwells and Pwells. Both of 
 these kinds of layout approaches attempt to lower the ß of either the vertical PNP or the lateral NPN  these kinds of layout approaches attempt to lower the ß of either the vertical PNP or the lateral NPN 
 parasitic bipolar transistors to less than 1. Some of these methods also tend to lower the resistance of  parasitic bipolar transistors to less than 1. Some of these methods also tend to lower the resistance of 
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 the SCR. the SCR.
  
-**For Further Reading:**+<WRAP round download> 
 +**Resources:** 
 +  * Fritzing files: [[downgit>education_tools/tree/master/m2k/fritzing/silicon_ctrl_rectifier_bb | silicon_ctrl_rectifier_bb ]] 
 +  * LTspice files: [[downgit>education_tools/tree/master/m2k/ltspice/silicon_ctrl_rectifier_ltspice | silicon_ctrl_rectifier_ltspice ]] 
 +</WRAP>
  
-http://en.wikipedia.org/wiki/Silicon-controlled_rectifier+=====The Programmable UJT (PUT)=====
  
-[[http://www.analog.com/static/imported-files/application_notes/AN-397.pdf| Electrically Induced Damage to Standard Linear Integrated Circuits]]+The Programmable unijunction transistor or PUT is a close relative of other four layer devices in the thyristor family. Its has a four layered construction just like the SCR and has three terminals named anode(A), cathode(K) and gate(G) again like the thyristors. Background and example circuits that use the PUT can be found in this [[:university:courses:alm1k:alm-lab-scr#programmable_ujt_put|ADALM1000 Lab Activity]]. 
 + 
 +**For Further Reading:**
  
-[[http://www.analog.com/library/analogDialogue/archives/35-05/latchup/latchup.pdf|Winning the Battle Against Latch-up in CMOS Analog Switches]]+[[http://en.wikipedia.org/wiki/Silicon-controlled_rectifier|The Silicon Controlled Rectifier]]\\ 
 +[[adi>static/imported-files/application_notes/AN-397.pdf| Electrically Induced Damage to Standard Linear Integrated Circuits]]\\ 
 +[[adi>library/analogDialogue/archives/35-05/latchup/latchup.pdf|Winning the Battle Against Latch-up in CMOS Analog Switches]]
  
 **Return to Lab Activity [[university:courses:electronics:labs|Table of Contents]].** **Return to Lab Activity [[university:courses:electronics:labs|Table of Contents]].**
  
  
university/courses/electronics/electronics-lab-scr.1500905448.txt.gz · Last modified: 24 Jul 2017 16:10 by Antoniu Miclaus

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