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university:courses:electronics:electronics-lab-29 [05 Mar 2019 12:37] – [Alternate component choices:] Antoniu Miclausuniversity:courses:electronics:electronics-lab-29 [06 Sep 2022 08:58] (current) – Antoniu Miclaus
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 =====Background:===== =====Background:=====
  
-To construct the logic functions in this lab activity you will be using the CD4007 CMOS array and discrete NMOS and PMOS transistors (ZVN2110A NMOS and ZVP2110A PMOS) from the ADALP2000 Analog Parts Kit. The CD4007 consists of 3 pairs of complimentary MOSFETs, as shown in figure 1. Each pair shares a common gate (pins 6,3,10). The substrates of all PMOSFETs are common (positive supply pin 14), as well as those of the NMOSFETs (ground pin 7). For the left pair, the NMOS Source terminal is tied to the NMOS substrate (pin 7), and the PMOS Source terminal is tied to PMOS substrate (pin 14). The other two pairs are more general purpose. For the right pair, the Drain terminal of the NMOS is tied to the  +To construct the logic functions in this lab activity you will be using the CD4007 CMOS array and discrete NMOS and PMOS transistors (ZVN2110A NMOS and ZVP2110A PMOS) from the ADALP2000 Analog Parts Kit. The CD4007 consists of 3 pairs of complimentary MOSFETs, as shown in figure 1. Each pair shares a common gate (pins 6,3,10). The substrates of all PMOSFETs are common (positive supply pin 14), as well as those of the NMOSFETs (ground pin 7). For the left pair, the NMOS Source terminal is tied to the NMOS substrate (pin 7), and the PMOS Source terminal is tied to PMOS substrate (pin 14). The other two pairs are more general purpose. For the right pair, the Drain terminal of the NMOS is tied to the to the Drain terminal of the PMOS on pin 12.  
  
-{{ :university:courses:electronics:cd4007.png?400 |}}+{{ :university:courses:alm1k:cd4007_pinout.png?400 |}}
  
 <WRAP centeralign> Figure 1: CD4007 functional diagram. </WRAP> <WRAP centeralign> Figure 1: CD4007 functional diagram. </WRAP>
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 <WRAP centeralign> Figure 5 Scopy screenshot </WRAP> <WRAP centeralign> Figure 5 Scopy screenshot </WRAP>
  
-Now configure both AWG channels as square waves with 5 V amplitudes. Set AWG1 to a frequency of 1 KHz and AWG2 to a frequency of 2 KHz or twice AWG1. Set the phase of AWG2 to 0 degrees. Be sure to set the AWGs to run synchronously.+Now configure both AWG channels as square waves with 5 V amplitudes peak-to-peak. Set AWG1 to a frequency of 1 KHz and AWG2 to a frequency of 2 KHz or twice AWG1. Set the phase of AWG2 to 0 degrees. Be sure to set the AWGs to run synchronously.
  
 Observe the Q output on the scope screen with respect to the signals seen at the CLK and D inputs. Capture the various waveforms and save a screen shot for inclusion in your lab report. Observe the Q output on the scope screen with respect to the signals seen at the CLK and D inputs. Capture the various waveforms and save a screen shot for inclusion in your lab report.
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 <WRAP round download> <WRAP round download>
 **Resources:** **Resources:**
-  * Fritzing files: [[ https://minhaskamal.github.io/DownGit/#/home?url=https://github.com/analogdevicesinc/education_tools/tree/master/m2k/fritzing/cmos_dtype_latch_bb | cmos_dtype_latch_bb]] +  * Fritzing files: [[downgit>education_tools/tree/master/m2k/fritzing/cmos_dtype_latch_bb | cmos_dtype_latch_bb]] 
-  * LTSpice files: [[ https://minhaskamal.github.io/DownGit/#/home?url=https://github.com/analogdevicesinc/education_tools/tree/master/m2k/ltspice/cmos_dtype_latch_ltspice | cmos_dtype_latch_ltspice]]+  * LTSpice files: [[downgit>education_tools/tree/master/m2k/ltspice/cmos_dtype_latch_ltspice | cmos_dtype_latch_ltspice]]
 </WRAP> </WRAP>
  
 **For Further Reading:** **For Further Reading:**
  
-Electronic Latches [[http://en.wikipedia.org/wiki/Flip-flop_(electronics)]]+Electronic Latches [[wp>Flip-flop_(electronics)]]
  
 **Return to Lab Activity [[university:courses:electronics:labs|Table of Contents]].** **Return to Lab Activity [[university:courses:electronics:labs|Table of Contents]].**
university/courses/electronics/electronics-lab-29.txt · Last modified: 06 Sep 2022 08:58 by Antoniu Miclaus

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