| Both sides previous revisionPrevious revisionNext revision | Previous revision |
| university:courses:electronics:electronics-lab-27 [24 Apr 2017 08:50] – rename Antoniu Miclaus | university:courses:electronics:electronics-lab-27 [08 Jul 2022 15:36] (current) – [Background:] Doug Mercer |
|---|
| ====== Activity: TTL inverter and NAND gate ====== | ======Activity: TTL inverter and NAND gate, For ADALM2000====== |
| |
| ===== Objectives: ===== | ===== Objectives: ===== |
| <WRAP centeralign> Figure 1 TTL Inverter </WRAP> | <WRAP centeralign> Figure 1 TTL Inverter </WRAP> |
| |
| The input stage transistor Q<sub>1</sub> performs a current steering function. It can be thought of as a back-to-back diode arrangement. The transistor is operated in either forward or reverse mode to steer current to or from the second stage transistor's base, Q<sub>2</sub>. The forward current gain or ß<sub>F</sub>, is much larger than the reverse ß<sub>R</sub>. it provides a higher discharge current to discharge the base of when turning it off. | The input stage transistor Q<sub>1</sub> performs a current steering function. It can be thought of as a back-to-back diode arrangement. The transistor is operated in either forward or reverse mode to steer current to or from the second stage transistor's base, Q<sub>2</sub>. The forward current gain or ß<sub>F</sub>, is much larger than the reverse ß<sub>R</sub>. it provides a higher discharge current to discharge the base when turning it off. |
| |
| {{ :university:courses:electronics:a27_f2.png?500 |}} | {{ :university:courses:electronics:a27_f2.png?500 |}} |
| <WRAP centeralign> Figure 2 Equivalent circuit of input current steering stage </WRAP> | <WRAP centeralign> Figure 2 Equivalent circuit of input current steering stage </WRAP> |
| |
| Second stage transistor, Q<sub>2</sub> in figure 1, is a phase splitter driving transistor to drive both halves of the pull up and pull down output stage. It allows the input condition to be produced in opposite phases so that the output transistors can be driven in anti-phase. This allows Q<sub>3</sub> to be on when Q<sub>4</sub> is off and vice versa as shown in figure 3. | Second stage transistor, Q<sub>2</sub> in figure 1, is a phase splitter transistor to drive both halves of the pull up and pull down output stage. It allows the input condition to be produced in opposite phases so that the output transistors can be driven in anti-phase. This allows Q<sub>3</sub> to be on when Q<sub>4</sub> is off and vice versa as shown in figure 3. |
| |
| {{ :university:courses:electronics:a27_f3.png?500 |}} | {{ :university:courses:electronics:a27_f3.png?500 |}} |
| <WRAP centeralign> Figure 4 Output Stage </WRAP> | <WRAP centeralign> Figure 4 Output Stage </WRAP> |
| |
| The diode, D<sub>1</sub>, serves to increase the effective turn on voltage of Q<sub>4</sub> which allows it to be turned off before Q<sub>3</sub>turns fully on. This helps prevent potentially large surge currents from flowing in the output stage during transitions between logic states. Resistor R<sub>4</sub> also serves to limit the current that is allowed to flow in the output stage. The disadvantage is that the logic high voltage is reduced by an amount of the diode drop as shown in figure 6. | The diode, D<sub>1</sub>, serves to increase the effective turn on voltage of Q<sub>4</sub> which allows it to be turned off before Q<sub>3</sub>turns fully on. This helps prevent potentially large surge currents from flowing in the output stage during transitions between logic states. Resistor R<sub>4</sub> also serves to limit the current that is allowed to flow in the output stage. The disadvantage is that the logic high voltage is reduced by an amount of the diode drop as shown in figure 7. |
| ===== Materials: ===== | ===== Materials: ===== |
| ADALM2000 Active Learning Module\\ | ADALM2000 Active Learning Module\\ |
| 1 - 100 Ω Resistor\\ | 1 - 100 Ω Resistor\\ |
| 1 - small signal diode (1N914)\\ | 1 - small signal diode (1N914)\\ |
| 5 - small signal NPN transistors (2N3904 and SSM2212) | 5 - small signal NPN transistors (2N3904) |
| |
| ===== Directions: ===== | =====TTL Inverter===== |
| | ==== Directions: ==== |
| |
| Build the circuit shown in figure 5 on your solder-less bread board. The NPN transistors normally supplied with your ADALP2000 Analog Parts Kit are limited to 3 2N3904 and 1 SSM2212 matched pair. The SSM2212 device cannot be used for the input device(s) Q<sub>1</sub> (a,b) because it contains internal protection diodes across the base and emitter terminals to prevent them from being reverse biased. The SSM2212 NPN pair can be used for the output stage devices Q<sub>3</sub> and Q<sub>4</sub>. Use the 3 2N3904 transistors for Q<sub>1</sub> (a,b) and Q<sub>2</sub>. | Build the circuit shown in figure 5 on your solder-less bread board. The NPN transistors supplied with your ADALP2000 Parts Kit are limited to 5 2N3904 and 1 TIP31 power transistor. Use the 5 2N3904 transistors and a 1N914 diode. |
| | First, connect the TTL inverter circuit on your breadboard. |
| |
| | {{ :university:courses:electronics:a27_f5a.png?550 |}} |
| | |
| | <WRAP centeralign> Figure 5 TTL Inverter </WRAP> |
| | ==== Hardware Setup: ==== |
| | Connect your circuit to the ADALM2000 I/O connector as indicated by the green boxes. It is best to ground the unused negative scope inputs when not being used. The breadboard connections are shown in figure below. |
| | {{ :university:courses:electronics:a27f6a.png? |}} |
| | |
| | <WRAP centeralign> Figure 6 TTL Inverter Breadboard Circuit</WRAP> |
| | ==== Procedure: ==== |
| | Configure waveform generators, W1, with 100 Hz triangle wave with 0 V offset and 6 V amplitude peak-to-peak peak-to-peak values. Use the oscilloscope in the x-y mode to observe the voltage-transfer curve of the circuit. |
| | {{ :university:courses:electronics:a27_f7.png?500 |}} |
| | |
| | <WRAP centeralign> Figure 7 TTL inverter transfer curve</WRAP> |
| | =====TTL NAND Gate==== |
| | ==== Directions: ==== |
| | By adding another input to the TTL inverter, a TTL NAND gate can be made. Connect the TTL inverter circuit, shown on figure 8. |
| {{ :university:courses:electronics:a27_f5.png?550 |}} | {{ :university:courses:electronics:a27_f5.png?550 |}} |
| |
| <WRAP centeralign> Figure 5 TTL inverter / two input NAND gate </WRAP> | <WRAP centeralign> Figure 8 TTL two input NAND Gate </WRAP> |
| |
| ===== Measurements: ===== | ==== Hardware Setup: ==== |
| | Connect your circuit to the ADALM2000 I/O connector as indicated by the green boxes. It is best to ground the unused negative scope inputs when not being used. The breadboard connections are shown in figure below. |
| | {{ :university:courses:electronics:a27f9.png? |}} |
| |
| ==== Transfer Characteristic: ==== | <WRAP centeralign> Figure 9 TTL two input NAND Gate Breadboard Circuit </WRAP> |
| | ==== Procedure: ==== |
| | Configure waveform generators, W1, with 100 Hz triangle wave with 0 V offset and 6 V amplitude peak-to-peak values and W2, 100 Hz triangle wave with 0 V offset and 6 V amplitude peak-to-peak values and 90° phase. Use the oscilloscope to observe the output of the circuit, CH2. |
| | {{ :university:courses:electronics:a27_f10.png?550 |}} |
| | |
| | <WRAP centeralign> Figure 10 TTL NAND Gate Output Waveform </WRAP> |
| | |
| | ===== Measurements: ===== |
| | <hidden> |
| | **Transfer Characteristic:** |
| |
| The transfer characteristic can be deduced by applying a slowly ramping input voltage and determining the sequence of events which takes place with respect to changes in the states of conduction of each transistor and the critical points at which the onset of these changes happen. Consider the circuit input vs. output transfer characteristic curve shown in figure 6. | The transfer characteristic of a TTL inverter can be deduced by applying a slowly ramping input voltage and determining the sequence of events which takes place with respect to changes in the states of conduction of each transistor and the critical points at which the onset of these changes happen. Consider the circuit input vs. output transfer characteristic curve shown in figure 6. |
| |
| {{ :university:courses:electronics:a27_f6.png?500 |}} | {{ :university:courses:electronics:a27_f6.png?500 |}} |
| <WRAP centeralign> Figure 6 TTL inverter input vs output transfer curve </WRAP> | <WRAP centeralign> Figure 6 TTL inverter input vs output transfer curve </WRAP> |
| |
| ==== Break Point P1 ==== | **Break Point P1** |
| |
| With the input near 0 volts and the base current supplied to Q<sub>1</sub>, this transistor can conduct in the forward mode. Since the only source of collector current is the leakage of Q<sub>2</sub> , Q<sub>1</sub> will be driven into saturation. This ensures that Q<sub>2</sub> is off which, in turn, means that Q<sub>3</sub> is off. While there is no load present, there are leakage currents flowing in the output stage which allow the transistor Q<sub>4</sub> and the diode D<sub>1</sub> to be barely conducting in the ON state. | With the input near 0 volts and the base current supplied to Q<sub>1</sub>, this transistor can conduct in the forward mode. Since the only source of collector current is the leakage of Q<sub>2</sub>, Q<sub>1</sub> will be driven into saturation. This ensures that Q<sub>2</sub> is off which, in turn, means that Q<sub>3</sub> is off. While there is no load present, there are leakage currents flowing in the output stage which allow the transistor Q<sub>4</sub> and the diode D<sub>1</sub> to be barely conducting in the ON state. |
| |
| **V<sub>OUT</sub> = V<sub>CC</sub> - V<sub>BE4</sub> - V<sub>D1</sub>**\\ | **V<sub>OUT</sub> = V<sub>CC</sub> - V<sub>BE4</sub> - V<sub>D1</sub>**\\ |
| **Point P1: V<sub>IN</sub> = 0.5, V<sub>OUT</sub> = 3.8V**\\ | **Point P1: V<sub>IN</sub> = 0.5, V<sub>OUT</sub> = 3.8V**\\ |
| |
| ==== Break Point P2 ==== | **Break Point P2** |
| |
| As the input voltage is slightly increased, the above state continues until, with Q<sub>1</sub> on and in saturation, the voltage at the base of Q<sub>2</sub> rises to the point of conduction. Then: | As the input voltage is slightly increased, the above state continues until, with Q<sub>1</sub> on and in saturation, the voltage at the base of Q<sub>2</sub> rises to the point of conduction. Then: |
| **Point P2: V<sub>IN</sub> = 0.5, V<sub>OUT</sub> = 3.8V**\\ | **Point P2: V<sub>IN</sub> = 0.5, V<sub>OUT</sub> = 3.8V**\\ |
| |
| ==== Break Point P3 ==== | **Break Point P3** |
| |
| As the input voltage is further increased, Q<sub>2</sub> becomes more conducting, turning fully ON. Base current to Q<sub>2</sub> is supplied by the now forward biased base-collector junction of Q<sub>1</sub> which is still in saturation. Eventually, Q<sub>3</sub> reaches the point of conduction. This happens when: | As the input voltage is further increased, Q<sub>2</sub> becomes more conducting, turning fully ON. Base current to Q<sub>2</sub> is supplied by the now forward biased base-collector junction of Q<sub>1</sub> which is still in saturation. Eventually, Q<sub>3</sub> reaches the point of conduction. This happens when: |
| **Point 3: V<sub>i</sub> = 1.2V, V<sub>O</sub> = 2.81V**\\ | **Point 3: V<sub>i</sub> = 1.2V, V<sub>O</sub> = 2.81V**\\ |
| |
| ==== Break Point P4 ==== | **Break Point P4** |
| |
| As the input voltage is further increased, Q<sub>2</sub> conducts more heavily, eventually saturating. Q<sub>3</sub> also conducts more heavily and eventually reaches the point of saturation also. As Q<sub>2</sub> becomes more conducting, its collector current increases. This in turn increases the voltage drop across R<sub>1</sub> which in turn means that the voltage across Q<sub>2</sub> i.e. V<sub>CE2</sub> drops. This falls below the requirement for conduction in Q<sub>4</sub> and the diode, D<sub>1</sub>, so that both of these turn OFF prior to the saturation of Q<sub>3</sub>. | As the input voltage is further increased, Q<sub>2</sub> conducts more heavily, eventually saturating. Q<sub>3</sub> also conducts more heavily and eventually reaches the point of saturation also. As Q<sub>2</sub> becomes more conducting, its collector current increases. This in turn increases the voltage drop across R<sub>1</sub> which in turn means that the voltage across Q<sub>2</sub> i.e. V<sub>CE2</sub> drops. This falls below the requirement for conduction in Q<sub>4</sub> and the diode, D<sub>1</sub>, so that both of these turn OFF prior to the saturation of Q<sub>3</sub>. |
| **V<sub>i</sub> = V<sub>BE2</sub> + V<sub>BE3</sub> - V<sub>CE1</sub>**\\ | **V<sub>i</sub> = V<sub>BE2</sub> + V<sub>BE3</sub> - V<sub>CE1</sub>**\\ |
| **V<sub>i</sub> = 0.7 + 0.7 - 0.1 = 1.5V**\\ | **V<sub>i</sub> = 0.7 + 0.7 - 0.1 = 1.5V**\\ |
| **Point 4: V<sub>i</sub> = 1.4V, V<sub>O</sub> = 0.2V**\\ | **Point 4: V<sub>i</sub> = 1.4V, V<sub>O</sub> = 0.2V**\\</hidden> |
| |
| ===== Questions: ===== | ===== Questions: ===== |
| The output circuitry of a typical TTL logic gate is commonly referred to a totem-pole output because the two output transistors are stacked one above the other like carvings on a totem pole. Is a gate circuit with a totem-pole output stage able to source load current, sink load current, or do both? | The output circuitry of a typical TTL logic gate is commonly referred to a totem-pole output because the two output transistors are stacked one above the other like carvings on a totem pole. Is a gate circuit with a totem-pole output stage able to source load current, sink load current, or do both? |
| |
| | <WRAP round download> |
| | *Resources:* |
| | * Fritzing files: [[downgit>education_tools/tree/master/m2k/fritzing/ttl_inv_and_nand_bb | ttl_inv_and_nand_bb ]] |
| | * LTspice files: [[downgit>education_tools/tree/master/m2k/ltspice/ttl_inv_and_nand_ltspice | ttl_inv_and_nand_ltspice ]] |
| | </WRAP> |
| =====For Further Reading:===== | =====For Further Reading:===== |
| |
