A variety of digital logic circuit techniques have been in use since the 1960s, when integrated logic gates were first produced. In this Lab activity, the Transistor Transistor Logic (TTL) circuit inverter (NOT gate) and 2 input NAND gate configurations are examined.
The schematic of a Transistor Transistor Logic (TTL) inverter is shown in figure 1. This circuit overcomes the limitations of the single transistor inverter circuit. The basic TTL inverter consists of three stages. A current steering input, a phase splitting stage and an output driver stage.
Figure 1 TTL Inverter
The input stage transistor Q1 performs a current steering function. It can be thought of as a back-to-back diode arrangement. The transistor is operated in either forward or reverse mode to steer current to or from the second stage transistor's base, Q2. The forward current gain or ßF, is much larger than the reverse ßR. it provides a higher discharge current to discharge the base of when turning it off.
Figure 2 Equivalent circuit of input current steering stage
Second stage transistor, Q2 in figure 1, is a phase splitter driving transistor to drive both halves of the pull up and pull down output stage. It allows the input condition to be produced in opposite phases so that the output transistors can be driven in anti-phase. This allows Q3 to be on when Q4 is off and vice versa as shown in figure 3.
Figure 3 Phase splitting stage
The output transistor pair, Q3 and Q4 along with diode D1 are referred to as a totem-pole output as shown in figure 4. This output configuration provides the ability to both actively source or sink current and is useful for driving capacitive loads. Resistor R4, serves to limit the current available from VCC. Under steady-state conditions, only one transistor is on at a time.
Figure 4 Output Stage
The diode, D1, serves to increase the effective turn on voltage of Q4 which allows it to be turned off before Q3turns fully on. This helps prevent potentially large surge currents from flowing in the output stage during transitions between logic states. Resistor R4 also serves to limit the current that is allowed to flow in the output stage. The disadvantage is that the logic high voltage is reduced by an amount of the diode drop as shown in figure 6.
ADALM2000 Active Learning Module
1 - 100 KΩ Resistor
1 - 2.2 KΩ Resistor
1 - 470 Ω Resistor
1 - 100 Ω Resistor
1 - small signal diode (1N914)
5 - small signal NPN transistors (2N3904 and SSM2212)
Build the circuit shown in figure 5 on your solder-less bread board. The NPN transistors normally supplied with your ADALP2000 Analog Parts Kit are limited to 3 2N3904 and 1 SSM2212 matched pair. The SSM2212 device cannot be used for the input device(s) Q1 (a,b) because it contains internal protection diodes across the base and emitter terminals to prevent them from being reverse biased. The SSM2212 NPN pair can be used for the output stage devices Q3 and Q4. Use the 3 2N3904 transistors for Q1 (a,b) and Q2.
Figure 5 TTL inverter / two input NAND gate
The transfer characteristic can be deduced by applying a slowly ramping input voltage and determining the sequence of events which takes place with respect to changes in the states of conduction of each transistor and the critical points at which the onset of these changes happen. Consider the circuit input vs. output transfer characteristic curve shown in figure 6.
Figure 6 TTL inverter input vs output transfer curve
With the input near 0 volts and the base current supplied to Q1, this transistor can conduct in the forward mode. Since the only source of collector current is the leakage of Q2 , Q1 will be driven into saturation. This ensures that Q2 is off which, in turn, means that Q3 is off. While there is no load present, there are leakage currents flowing in the output stage which allow the transistor Q4 and the diode D1 to be barely conducting in the ON state.
VOUT = VCC - VBE4 - VD1
VOUT = 5 - 0.6 - 0.6 = 3.8V
Point P1: VIN = 0.5, VOUT = 3.8V
As the input voltage is slightly increased, the above state continues until, with Q1 on and in saturation, the voltage at the base of Q2 rises to the point of conduction. Then:
VIN = VBE2 - VCE1(SAT) = 0.6 - 0.1 = 0.5
Point P2: VIN = 0.5, VOUT = 3.8V
As the input voltage is further increased, Q2 becomes more conducting, turning fully ON. Base current to Q2 is supplied by the now forward biased base-collector junction of Q1 which is still in saturation. Eventually, Q3 reaches the point of conduction. This happens when:
VIN = VBE2 + VBE3 - VCE1(SAT)
VIN = 0.7 + 0.6 - 0.1 = 1.2V
Note that with transistor Q3 just at turn on, VBE3 = 0.6V which means that the current through R3 is 0.6V/470Ω = 1.27mA. With operation in the linear active region, the collector current in Q2 is 0.97 × 1.27mA = 1.23mA. ˜ aF IE2
The voltage drop across R2 is then VR2 = 1.23mA × 2.2 kΩ = 2.7V.
Under this condition the collector to emitter voltage drop across Q2 is:
VCE2 = VCC - VR2 - VR3
VCE2 = 5 - 2.7 - 0.6 = 1.7V
This confirms that Q2 is still operating in the forward active mode.
With Q3 beginning to conduct there is a conduction path for current through Q4 and the diode, D1, which then turns fully ON. In this case:
VO = VCC - VR1 - VBE4 - VD1
VO = 5 - 0.94 - 0.65 - 0.6 = 2.81V
Point 3: Vi = 1.2V, VO = 2.81V
As the input voltage is further increased, Q2 conducts more heavily, eventually saturating. Q3 also conducts more heavily and eventually reaches the point of saturation also. As Q2 becomes more conducting, its collector current increases. This in turn increases the voltage drop across R1 which in turn means that the voltage across Q2 i.e. VCE2 drops. This falls below the requirement for conduction in Q4 and the diode, D1, so that both of these turn OFF prior to the saturation of Q3.
When Q3 reaches the edge of saturation:
Vi = VBE2 + VBE3 - VCE1
Vi = 0.7 + 0.7 - 0.1 = 1.5V
Point 4: Vi = 1.4V, VO = 0.2V
The output circuitry of a typical TTL logic gate is commonly referred to a totem-pole output because the two output transistors are stacked one above the other like carvings on a totem pole. Is a gate circuit with a totem-pole output stage able to source load current, sink load current, or do both?
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