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Activity: TTL inverter and NAND gate, For ADALM2000

Objectives:

A variety of digital logic circuit techniques have been in use since the 1960s, when integrated logic gates were first produced. In this Lab activity, the Transistor Transistor Logic (TTL) circuit inverter (NOT gate) and 2 input NAND gate configurations are examined.

Background:

The schematic of a Transistor Transistor Logic (TTL) inverter is shown in figure 1. This circuit overcomes the limitations of the single transistor inverter circuit. The basic TTL inverter consists of three stages. A current steering input, a phase splitting stage and an output driver stage.

Figure 1 TTL Inverter

The input stage transistor Q₁ performs a current steering function. It can be thought of as a back-to-back diode arrangement. The transistor is operated in either forward or reverse mode to steer current to or from the second stage transistor's base, Q₂. The forward current gain or ß_F, is much larger than the reverse ß_R. it provides a higher discharge current to discharge the base of when turning it off.

Figure 2 Equivalent circuit of input current steering stage

Second stage transistor, Q₂ in figure 1, is a phase splitter driving transistor to drive both halves of the pull up and pull down output stage. It allows the input condition to be produced in opposite phases so that the output transistors can be driven in anti-phase. This allows Q₃ to be on when Q₄ is off and vice versa as shown in figure 3.

Figure 3 Phase splitting stage

The output transistor pair, Q₃ and Q₄ along with diode D₁ are referred to as a totem-pole output as shown in figure 4. This output configuration provides the ability to both actively source or sink current and is useful for driving capacitive loads. Resistor R₄, serves to limit the current available from V_CC. Under steady-state conditions, only one transistor is on at a time.

Figure 4 Output Stage

The diode, D₁, serves to increase the effective turn on voltage of Q₄ which allows it to be turned off before Q₃turns fully on. This helps prevent potentially large surge currents from flowing in the output stage during transitions between logic states. Resistor R₄ also serves to limit the current that is allowed to flow in the output stage. The disadvantage is that the logic high voltage is reduced by an amount of the diode drop as shown in figure 6.

Materials:

ADALM2000 Active Learning Module
Solder-less breadboard
Jumper wires
1 - 100 KΩ Resistor
1 - 2.2 KΩ Resistor
1 - 470 Ω Resistor
1 - 100 Ω Resistor
1 - small signal diode (1N914)
5 - small signal NPN transistors (2N3904 and SSM2212)

TTL Inverter

Directions:

The NPN transistors normally supplied with your ADALP2000 Analog Parts Kit are limited to 3 2N3904 and 1 SSM2212 matched pair. The SSM2212 device cannot be used for the input device(s) Q₁ (a,b) because it contains internal protection diodes across the base and emitter terminals to prevent them from being reverse biased. The SSM2212 NPN pair can be used for the output stage devices Q₃ and Q₄. Use the 3 2N3904 transistors for Q₁ (a,b) and Q₂. First, connect the TTL inverter circuit on your breadboard.

Figure 5 TTL Inverter

Hardware Setup:

Connect your circuit to the ADALM2000 I/O connector as indicated by the green boxes. It is best to ground the unused negative scope inputs when not being used. The breadboard connections are shown in figure below.

Figure 6 TTL Inverter Breadboard Circuit

Procedure:

Configure waveform generators, W1, with 100 Hz triangle wave with 0 V offset and 6 V amplitude peak-to-peak peak-to-peak values. Use the oscilloscope in the x-y mode to observe the voltage-transfer curve of the circuit.

Figure 7 TTL inverter transfer curve

TTL NAND Gate

Directions:

By adding another input to the TTL inverter, a TTL NAND gate can be made. Connect the TTL inverter circuit, shown on figure 8.

Figure 8 TTL two input NAND Gate

Hardware Setup:

Connect your circuit to the ADALM2000 I/O connector as indicated by the green boxes. It is best to ground the unused negative scope inputs when not being used. The breadboard connections are shown in figure below.

Figure 9 TTL two input NAND Gate Breadboard Circuit

Procedure:

Configure waveform generators, W1, with 100 Hz triangle wave with 0 V offset and 6 V amplitude peak-to-peak values and W2, 100 Hz triangle wave with 0 V offset and 6 V amplitude peak-to-peak values and 90° phase. Use the oscilloscope to observe the output of the circuit, CH2.

Figure 10 TTL NAND Gate Output Waveform

Measurements:

Click to display ⇲

Click to hide ⇱

Transfer Characteristic:

The transfer characteristic of a TTL inverter can be deduced by applying a slowly ramping input voltage and determining the sequence of events which takes place with respect to changes in the states of conduction of each transistor and the critical points at which the onset of these changes happen. Consider the circuit input vs. output transfer characteristic curve shown in figure 6.

Figure 6 TTL inverter input vs output transfer curve

Break Point P1

With the input near 0 volts and the base current supplied to Q₁, this transistor can conduct in the forward mode. Since the only source of collector current is the leakage of Q₂, Q₁ will be driven into saturation. This ensures that Q₂ is off which, in turn, means that Q₃ is off. While there is no load present, there are leakage currents flowing in the output stage which allow the transistor Q₄ and the diode D₁ to be barely conducting in the ON state.

V_OUT = V_CC - V_BE4 - V_D1
V_OUT = 5 - 0.6 - 0.6 = 3.8V
Point P1: V_IN = 0.5, V_OUT = 3.8V

Break Point P2

As the input voltage is slightly increased, the above state continues until, with Q₁ on and in saturation, the voltage at the base of Q₂ rises to the point of conduction. Then:

V_IN = V_BE2 - V_CE1(SAT) = 0.6 - 0.1 = 0.5
Point P2: V_IN = 0.5, V_OUT = 3.8V

Break Point P3

As the input voltage is further increased, Q₂ becomes more conducting, turning fully ON. Base current to Q₂ is supplied by the now forward biased base-collector junction of Q₁ which is still in saturation. Eventually, Q₃ reaches the point of conduction. This happens when:

V_IN = V_BE2 + V_BE3 - V_CE1(SAT)
V_IN = 0.7 + 0.6 - 0.1 = 1.2V

Note that with transistor Q₃ just at turn on, V_BE3 = 0.6V which means that the current through R₃ is 0.6V/470Ω = 1.27mA. With operation in the linear active region, the collector current in Q₂ is 0.97 × 1.27mA = 1.23mA. ˜ a_F I_E2

The voltage drop across R₂ is then V_R2 = 1.23mA × 2.2 kΩ = 2.7V.

Under this condition the collector to emitter voltage drop across Q₂ is:

V_CE2 = V_CC - V_R2 - V_R3
V_CE2 = 5 - 2.7 - 0.6 = 1.7V

This confirms that Q₂ is still operating in the forward active mode.

With Q₃ beginning to conduct there is a conduction path for current through Q₄ and the diode, D₁, which then turns fully ON. In this case:

V_O = V_CC - V_R1 - V_BE4 - V_D1
V_O = 5 - 0.94 - 0.65 - 0.6 = 2.81V
Point 3: V_i = 1.2V, V_O = 2.81V

Break Point P4

As the input voltage is further increased, Q₂ conducts more heavily, eventually saturating. Q₃ also conducts more heavily and eventually reaches the point of saturation also. As Q₂ becomes more conducting, its collector current increases. This in turn increases the voltage drop across R₁ which in turn means that the voltage across Q₂ i.e. V_CE2 drops. This falls below the requirement for conduction in Q₄ and the diode, D₁, so that both of these turn OFF prior to the saturation of Q₃.

When Q₃ reaches the edge of saturation:

V_i = V_BE2 + V_BE3 - V_CE1
V_i = 0.7 + 0.7 - 0.1 = 1.5V
Point 4: V_i = 1.4V, V_O = 0.2V\\

Questions:

The output circuitry of a typical TTL logic gate is commonly referred to a totem-pole output because the two output transistors are stacked one above the other like carvings on a totem pole. Is a gate circuit with a totem-pole output stage able to source load current, sink load current, or do both?

*Resources:*

Fritzing files: ttl_inv_and_nand_bb
LTspice files: ttl_inv_and_nand_ltspice

For Further Reading:

http://en.wikipedia.org/wiki/Transistor-transistor_logic

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Table of Contents

Activity: TTL inverter and NAND gate, For ADALM2000

Objectives:

Background:

Materials:

TTL Inverter

Directions:

Hardware Setup:

Procedure:

TTL NAND Gate

Directions:

Hardware Setup:

Procedure:

Measurements:

Questions:

For Further Reading:

Analog Devices Wiki

Table of Contents

Activity: TTL inverter and NAND gate, For ADALM2000

Objectives:

Background:

Materials:

TTL Inverter

Directions:

Hardware Setup:

Procedure:

TTL NAND Gate

Directions:

Hardware Setup:

Procedure:

Measurements:

Questions:

For Further Reading:

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