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university:courses:electronics:electronics-lab-14 [15 Sep 2013 15:30] – created Doug Merceruniversity:courses:electronics:electronics-lab-14 [15 Nov 2017 08:05] – Trecia Agoylo
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 =====Background:===== =====Background:=====
  
-We will exploit the simple CMOS inverter logic gate as a pair of switches. The digital I/O signals of the Analog Discovery module can be configured as standard CMOS dividers with a +3.3 Volt supply (push-pull mode). In the simplest form, a CMOS output consists of one PMOS device, M<sub>1</sub> and one NMOS device M<sub>2</sub>. Generally the CMOS fabrication process is designed such that the threshold voltage, V<sub>TH</sub>, of the NMOS and PMOS devices are roughly equal i.e. complementary. The designer of the inverter then adjusts the width to length ratio, W/L, of the NMOS and PMOS devices such that their respective transconductance and thus their R<sub>ON</sub>, is also equal. Only one of the two transistors is ever on at the same time connecting the Output to either V<sub>DD</sub> or V<sub>SS</sub>. We can consider these two voltages to be the reference for out DAC.+We will exploit the simple CMOS inverter logic gate as a pair of switches. The digital I/O signals of the ADALM2000 module can be configured as standard CMOS dividers with a +3.3 Volt supply (push-pull mode). In the simplest form, a CMOS output consists of one PMOS device, M<sub>1</sub> and one NMOS device M<sub>2</sub>. Generally the CMOS fabrication process is designed such that the threshold voltage, V<sub>TH</sub>, of the NMOS and PMOS devices are roughly equal i.e. complementary. The designer of the inverter then adjusts the width to length ratio, W/L, of the NMOS and PMOS devices such that their respective transconductance and thus their R<sub>ON</sub>, is also equal. Only one of the two transistors is ever on at the same time connecting the Output to either V<sub>DD</sub> or V<sub>SS</sub>. We can consider these two voltages to be the reference for out DAC.
  
 {{ :university:courses:electronics:a14_f1.png?600 |}} {{ :university:courses:electronics:a14_f1.png?600 |}}
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 =====Materials:===== =====Materials:=====
- +ADALM2000 Active Learning Module\\
-Analog Discovery Lab hardware\\+
 Solder-less breadboard\\ Solder-less breadboard\\
 Jumper wires\\ Jumper wires\\
-9 - 20KΩ Resistors\\ +9 - 20 KΩ Resistors\\ 
-9 - 10KΩ Resistors\\+9 - 10 KΩ Resistors\\
 1 - OP27 amplifier 1 - OP27 amplifier
  
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 Connect the 8 digital outputs designated by the blue boxes, and the scope channel and AWG output designated by the green boxes to the resistor ladder circuit as shown. Remember to connect power to the op amp supply pins. Connect the 8 digital outputs designated by the blue boxes, and the scope channel and AWG output designated by the green boxes to the resistor ladder circuit as shown. Remember to connect power to the op amp supply pins.
  
-=====Hardware set up:=====+=====Hardware Setup:=====
  
-With both R<sub>1</sub> and R<sub>2</sub> installed, set AWG1 to a DC voltage equal to the V<sub>REF</sub>+ of the DAC which will be the +3.3 Volt supply voltage of the CMOS digital outputs. This will produce a bipolar output voltage which will swing from -3.3V to +3.3V. Disconnect AWG1 and remove resistor R<sub>1</sub> for a unipolar output voltage which will swing from 0 to +3.3V.+{{ :university:courses:electronics:a14_f2_bb.JPG? |}}
  
-Start the Waveforms software. Open up the Digital Patterns screen. Add a bus signal. Select DIO 0 - 7 and click on the right green arrow to add signals to the bus. Click on the show analog representation check box. Select the format to be binary and the endianness to be LSB. The MSB should be DIO 7 and the LSB should be DIO 0. Click on the OK button. Now edit the parameters for bus 0. The output should be PP (for push-pull) and set the frequency for 256KHz. Close the bus edit window. You should see something that looks like the screen below shown in figure 3. Lastly, hit the Run button. +<WRAP centeralign > Figure 3 R-2R Resistor Ladder Circuit Breadboard Connections </WRAP> 
 + 
 +=====Proceduce:===== 
 +With both R<sub>1</sub> and R<sub>2</sub> installed, set AWG1 to a DC voltage equal to the V<sub>REF</sub>+ of the DAC which will be the +3.3 Volt supply voltage of the CMOS digital outputs. This will produce a bipolar output voltage which will swing from -3.3V to +3.3V. Disconnect AWG1 and remove resistor R<sub>1</sub> for a unipolar output voltage which will swing from 0 to +3.3V. 
 +Start the Scopy software. Open up the Pattern Generator screen. Select and group DIO 0 - 7. Now edit the parameters. Set pattern to Binary counter. The output should be PP (for push-pull) and set the frequency for 256 KHz. You should see something that looks like the screen below shown in figure 4. Lastly, hit the Run button. 
  
 {{ :university:courses:electronics:a14_f3.jpg?600 |}} {{ :university:courses:electronics:a14_f3.jpg?600 |}}
  
-<WRAP centeralign > Figure 3 Pattern Generator screen </WRAP>+<WRAP centeralign > Figure 4 Pattern Generator screen </WRAP>
  
-Open the Scope screen, turn channel 1 on, and set the time base for 200us/div. Be sure to hit the green Run button. You may also need to adjust the vertical range for the channel 1 V/div is probably good to start with. You should see (figure 4) the voltage ramp up from 0 volts to 3.3 volts. The period of the ramp should be 1mSec.+Open the Scope screen, turn channel 2 on, and set the time base for 200us/div. Be sure to hit the green Run button. You may also need to adjust the vertical range for the channel 1 V/div is probably good to start with. You should see (figure 4) the voltage ramp up from 0 volts to 3.3 volts. The period of the ramp should be 1mSec.
  
 {{ :university:courses:electronics:a14_f4.jpg?600 |}} {{ :university:courses:electronics:a14_f4.jpg?600 |}}
  
-<WRAP centeralign > Figure 4 Scope screen </WRAP>+<WRAP centeralign > Figure 5 Scope screen </WRAP>
  
 Change the digital pattern. Try the Random pattern and open the FFT window on the scope. You can also load custom patterns by making a plain text csv file with a column of numbers ranging from 0 to 255 (for the 8 bit wide bus). Load your custom pattern and see what happens. Change the digital pattern. Try the Random pattern and open the FFT window on the scope. You can also load custom patterns by making a plain text csv file with a column of numbers ranging from 0 to 255 (for the 8 bit wide bus). Load your custom pattern and see what happens.
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 2. How much current will flow through this resistor network when input D6 is connected to 3.3 volts and D7 to ground? 2. How much current will flow through this resistor network when input D6 is connected to 3.3 volts and D7 to ground?
  
-1. Discuss which DAC topology had better linearity, and why you would (or would not) expect this to be the case.+3. Discuss which DAC topology had better linearity, and why you would (or would not) expect this to be the case.
  
-2. How would you expect these DACs to perform for high frequency inputs? For better high frequency components, would you want smaller or larger resistor values? Discuss the relative merits of choosing large or small resistors for the DAC.+4. How would you expect these DACs to perform for high frequency inputs? For better high frequency components, would you want smaller or larger resistor values? Discuss the relative merits of choosing large or small resistors for the DAC.
  
-3. One of the effects of reducing the size of the resistors is that the parasitic switch resistances could start to become significant relative to the resistors. What would the output levels be for a 3-bit Binary-Weighted Resistor DAC where the switch resistance in figure 1 was 0.25R?+5. One of the effects of reducing the size of the resistors is that the parasitic switch resistances could start to become significant relative to the resistors. What would the output levels be for a 3-bit Binary-Weighted Resistor DAC where the switch resistance in figure 1 was 0.25R?
  
-If you were going to design a 16-bit DAC for audio purposes (for a mp3 player output), how would the resistor tolerances affect the errors in the output for an R-2R ladder DAC?+6. If you were going to design a 16-bit DAC for audio purposes (for a mp3 player output), how would the resistor tolerances affect the errors in the output for an R-2R ladder DAC?
  
 ====For further reading:==== ====For further reading:====
university/courses/electronics/electronics-lab-14.txt · Last modified: 25 Jun 2020 22:07 by 127.0.0.1

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