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Activity 14: R-2R Resistor Ladder Digital to Analog Converter


The objective of this exercise is to explore the concepts of digital to analog conversion making use of the CMOS inverter as reference switches for a resistor ladder divider (used in DAC).


We will exploit the simple CMOS inverter logic gate as a pair of switches. The digital I/O signals of the Analog Discovery module can be configured as standard CMOS dividers with a +3.3 Volt supply (push-pull mode). In the simplest form, a CMOS output consists of one PMOS device, M1 and one NMOS device M2. Generally the CMOS fabrication process is designed such that the threshold voltage, VTH, of the NMOS and PMOS devices are roughly equal i.e. complementary. The designer of the inverter then adjusts the width to length ratio, W/L, of the NMOS and PMOS devices such that their respective transconductance and thus their RON, is also equal. Only one of the two transistors is ever on at the same time connecting the Output to either VDD or VSS. We can consider these two voltages to be the reference for out DAC.

Figure 1 CMOS output driver

When used in what is referred to as “voltage mode” legs the R-2R resistor ladder, figure 2, are alternately driven to either of 2 reference voltage levels based on the digital code (D0-7). Digital 0 for VREF- and digital 1 for VREF+. Depending on the digital input code VLADDER ( in figure 2 ) will be some fraction of the difference between the two reference levels. The negative of the two reference voltages (VREF-) is often ground (VSS). The positive reference voltage (VREF+) in our case here will be the positive supply (VDD) for the CMOS driver.


Analog Discovery Lab hardware
Solder-less breadboard
Jumper wires
9 - 20KΩ Resistors
9 - 10KΩ Resistors
1 - OP27 amplifier


Build the 8 bit resister ladder circuit shown in figure 2, preferably on your solder-less breadboard. The number of resistors normally supplied in the Analog Parts Kit is not sufficient to build the full 8 bit ladder. It is best to use 1% resistors for this project if you have access to them.

Figure 2 R-2R Resistor Ladder circuit

Connect the 8 digital outputs designated by the blue boxes, and the scope channel and AWG output designated by the green boxes to the resistor ladder circuit as shown. Remember to connect power to the op amp supply pins.

Hardware set up:

With both R1 and R2 installed, set AWG1 to a DC voltage equal to the VREF+ of the DAC which will be the +3.3 Volt supply voltage of the CMOS digital outputs. This will produce a bipolar output voltage which will swing from -3.3V to +3.3V. Disconnect AWG1 and remove resistor R1 for a unipolar output voltage which will swing from 0 to +3.3V.

Start the Waveforms software. Open up the Digital Patterns screen. Add a bus signal. Select DIO 0 - 7 and click on the right green arrow to add signals to the bus. Click on the show analog representation check box. Select the format to be binary and the endianness to be LSB. The MSB should be DIO 7 and the LSB should be DIO 0. Click on the OK button. Now edit the parameters for bus 0. The output should be PP (for push-pull) and set the frequency for 256KHz. Close the bus edit window. You should see something that looks like the screen below shown in figure 3. Lastly, hit the Run button.

Figure 3 Pattern Generator screen

Open the Scope screen, turn channel 1 on, and set the time base for 200us/div. Be sure to hit the green Run button. You may also need to adjust the vertical range for the channel 1 V/div is probably good to start with. You should see (figure 4) the voltage ramp up from 0 volts to 3.3 volts. The period of the ramp should be 1mSec.

Figure 4 Scope screen

Change the digital pattern. Try the Random pattern and open the FFT window on the scope. You can also load custom patterns by making a plain text csv file with a column of numbers ranging from 0 to 255 (for the 8 bit wide bus). Load your custom pattern and see what happens.

Here are some pre-made waveform files you can try:

Sine, Triangle, Gaussian pulse etc.


1. Using Ohm's law and the formula for resistors in parallel, what is the output voltage of the R-2R DAC when inputs D7 and D6 are connected to each combination of ground and 3.3 volts? Please present the results as a table.

2. How much current will flow through this resistor network when input D6 is connected to 3.3 volts and D7 to ground?

1. Discuss which DAC topology had better linearity, and why you would (or would not) expect this to be the case.

2. How would you expect these DACs to perform for high frequency inputs? For better high frequency components, would you want smaller or larger resistor values? Discuss the relative merits of choosing large or small resistors for the DAC.

3. One of the effects of reducing the size of the resistors is that the parasitic switch resistances could start to become significant relative to the resistors. What would the output levels be for a 3-bit Binary-Weighted Resistor DAC where the switch resistance in figure 1 was 0.25R?

If you were going to design a 16-bit DAC for audio purposes (for a mp3 player output), how would the resistor tolerances affect the errors in the output for an R-2R ladder DAC?

For further reading:

university/courses/electronics/electronics-lab-14.1379251859.txt.gz · Last modified: 15 Sep 2013 15:30 by Doug Mercer