Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
resources:quick-start:ad5791 [11 Apr 2013 18:41] – Edits, formatting, adding tables 6 and 7 Yuet Ngresources:quick-start:ad5791 [16 Apr 2013 16:18] (current) – text edits throughout Yuet Ng
Line 2: Line 2:
 ====== AD5781/AD5791 Quick Start Guide ====== ====== AD5781/AD5791 Quick Start Guide ======
 ** Single, 18-/20-Bit, Voltage Output DACs, SPI Interface ** ** Single, 18-/20-Bit, Voltage Output DACs, SPI Interface **
- 
-\\ 
-{{ :resources:quick-start:ad5781_ad5791_block_diagram.png?direct&500 |}} 
-\\ 
-\\ 
-<WRAP CENTERALIGN>//Figure 1. Functional Block Diagram//</WRAP> 
-<WRAP clear></WRAP> 
-\\ 
 ===== Features ===== ===== Features =====
-\\ 
   * High relative accuracy (INL): ±0.5 LSB maximum (18-bit [[adi>ad5781|AD5781]])   * High relative accuracy (INL): ±0.5 LSB maximum (18-bit [[adi>ad5781|AD5781]])
   * 1 ppm resolution, 1 ppm INL (20-bit [[adi>ad5791|AD5791]])   * 1 ppm resolution, 1 ppm INL (20-bit [[adi>ad5791|AD5791]])
Line 24: Line 15:
   * 35 MHz Schmitt triggered digital interface   * 35 MHz Schmitt triggered digital interface
   * 1.8 V compatible digital interface   * 1.8 V compatible digital interface
 +
 +===== Functional Block Diagram =====
 +{{ :resources:quick-start:ad5781_ad5791_block_diagram.png?direct&500 |}}
 +<WRAP CENTERALIGN>//Figure 1. //</WRAP>
 +<WRAP clear></WRAP>
 \\ \\
 ===== Pin Configuration ===== ===== Pin Configuration =====
-\\ 
 <WRAP CENTERALIGN>{{ :resources:quick-start:ad5781_ad5791_pin_configuration.png?direct&300 |}}</WRAP> <WRAP CENTERALIGN>{{ :resources:quick-start:ad5781_ad5791_pin_configuration.png?direct&300 |}}</WRAP>
-<WRAP CENTERALIGN>//Figure 2. 24-Lead LFCSP Pin Configuration// </WRAP>+<WRAP CENTERALIGN>//Figure 2. 20-Lead TSSOP Pin Configuration// </WRAP>
 <WRAP clear></WRAP> <WRAP clear></WRAP>
 \\ \\
Line 65: Line 60:
 ^/LDAC                ^/CLR                ^/RESET                ^Function  ^ ^/LDAC                ^/CLR                ^/RESET                ^Function  ^
 |X<sup>1</sup>        |X<sup>1</sup>    |0           |DAC in reset mode. The device cannot be programmed.| |X<sup>1</sup>        |X<sup>1</sup>    |0           |DAC in reset mode. The device cannot be programmed.|
-|X<sup>1</sup>        |X<sup>1</sup>    |⇑<sup>2</sup>           |DAC is turned to its power-on state. All registers are set to their default values.|+|X<sup>1</sup>        |X<sup>1</sup>    |⇑<sup>2</sup>           |DAC is returned to its power-on state. All registers are set to their default values.|
 |0                    |0            |1           |DAC register loaded with the clearcode register value and output set accordingly.| |0                    |0            |1           |DAC register loaded with the clearcode register value and output set accordingly.|
 |0                    |1            |1           |Output set according to the DAC register value.| |0                    |1            |1           |Output set according to the DAC register value.|
Line 89: Line 84:
 \\ \\
 {{ :resources:quick-start:ad5781_91_shift_register_contents.png?direct&700 |}} {{ :resources:quick-start:ad5781_91_shift_register_contents.png?direct&700 |}}
-<WRAP CENTERALIGN>//Figure 3. Input Shift Register Contents ([[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]])//</WRAP>+<WRAP CENTERALIGN>//Figure 3. Input Shift Register Contents //</WRAP>
  
 \\ \\
Line 114: Line 109:
 \\ \\
 {{ :resources:quick-start:ad5781_91_control_register.png?direct&700 |}} {{ :resources:quick-start:ad5781_91_control_register.png?direct&700 |}}
-<WRAP CENTERALIGN>//Figure 4. Control Register ([[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]])//</WRAP>+<WRAP CENTERALIGN>//Figure 4. Control Register //</WRAP>
 \\ \\
 \\ \\
Line 139: Line 134:
 |:::|0 (default)  |SDO pin enabled.  | |:::|0 (default)  |SDO pin enabled.  |
 |:::|1  |SDO pin disabled (tristate).  | |:::|1  |SDO pin disabled (tristate).  |
-|LIN COMP            |Linearity error compensation for varying reference input spans. Note that the reference input span options are 10 V and 20 V for the [[adi>ad5781|AD5781]]. See the [[adi>ad5781|AD5781]] data sheet for further details.||+|LIN COMP            |Linearity error compensation for varying reference input spans. Note that the reference input span options for the [[adi>ad5781|AD5781]] are: up to 10 V (0000) and 20 V (1100). See the [[adi>ad5781|AD5781]] data sheet for additional details.||
 |:::|**Setting**  |**Function**  | |:::|**Setting**  |**Function**  |
 |:::|0000 (default)  |Reference input span up to 10 V. | |:::|0000 (default)  |Reference input span up to 10 V. |
Line 156: Line 151:
 \\ \\
 {{ :resources:quick-start:ad5781_91_software_control_register.png?direct&700 |}} {{ :resources:quick-start:ad5781_91_software_control_register.png?direct&700 |}}
-<WRAP CENTERALIGN>//Figure 5. Software Control Register ([[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]])//</WRAP>+<WRAP CENTERALIGN>//Figure 5. Software Control Register //</WRAP>
 \\ \\
 \\ \\
 **Table 5. Software Control Register Functions** **Table 5. Software Control Register Functions**
 ^Bit Name            ^Description  ^ ^Bit Name            ^Description  ^
-|LDAC<sup>1</sup>                |Setting this bit to 1 updates the DAC register and consequently the DAC output.|            +|LDAC<sup>1</sup>                |Setting this bit to 1 updates the DAC register and, consequently, the DAC output.|            
 |CLR<sup>2</sup>               |Setting this bit to 1 sets the DAC register to a user defined value and updates the DAC output.| |CLR<sup>2</sup>               |Setting this bit to 1 sets the DAC register to a user defined value and updates the DAC output.|
 |RESET               |Setting this bit to 1 returns the [[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] to its power-on state.| |RESET               |Setting this bit to 1 returns the [[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] to its power-on state.|
-<sup>1</sup> The LDAC function has no effect when the <m>overline{CLR}</m> pin is low. Refer to Table 2 in the [[resources/quick-start/ad5791#hardware_control_pins_truth_table|Hardware Control Pins Truth Table]] section for further details.\\ +<sup>1</sup> The LDAC function has no effect when the <m>overline{CLR}</m> pin is low. Refer to Table 2 in the [[resources/quick-start/ad5791#hardware_control_pins_truth_table|Hardware Control Pins Truth Table]] section for additional details.\\ 
-<sup>2</sup> The CLR function has no effect when the <m>overline{LDAC}</m> pin is low. Refer to Table 2 in the [[resources/quick-start/ad5791#hardware_control_pins_truth_table|Hardware Control Pins Truth Table]] section for further details.+<sup>2</sup> The CLR function has no effect when the <m>overline{LDAC}</m> pin is low. Refer to Table 2 in the [[resources/quick-start/ad5791#hardware_control_pins_truth_table|Hardware Control Pins Truth Table]] section for additional details.
  
 \\ \\
Line 187: Line 182:
  
  To initialize the part,   To initialize the part, 
-  * Because this initialization is a write to the part, set the R/W bit to a Logic 0.+  * Because this initialization is a write to the part, set the R/<m>overline{W}</m> bit to a Logic 0.
   * Keep the default mode for LIN COMP, SDODIS, and RBUF.   * Keep the default mode for LIN COMP, SDODIS, and RBUF.
   * To write in binary coding, select BIN/2sC = 1.   * To write in binary coding, select BIN/2sC = 1.
-  * Set DACTRI = 0 and OPGND = 0  to remove the DAC output clamp to ground and place the DAC in normal operating mode. +  * Set DACTRI = 0 and OPGND = 0  to place the DAC in normal operating mode and remove the DAC output clamp to ground, respectively. 
  
-See Table 6 and Figure 6.+Write the following over the serial interface: 0010 0000 0000 0000 0001 0010 (R/<m>overline{W}</m> bit, three register address bits, 20 data bits).
 \\ \\
 \\ \\
-Write the following over the serial interface: 0010 0000 0000 0000 0001 0010 (R/<m>overline{W}</m> bit, three register address bits, 20 data bits).+See Table 6 and Figure 6.
 \\ \\
 \\ \\
Line 201: Line 196:
 ^Bit(s)  ^Bit Name  ^Setting  ^Description  ^ ^Bit(s)  ^Bit Name  ^Setting  ^Description  ^
 |23  |R/<m>overline{W}</m>  |0  |[[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] addressed for a write operation  | |23  |R/<m>overline{W}</m>  |0  |[[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] addressed for a write operation  |
 +|[22:20]  |C2, C1, C0  |010  |Write to the control register  |
 |[9:6]  |LIN COMP  |0000  |Linearity error compensation for a reference input span up to 10 V | |[9:6]  |LIN COMP  |0000  |Linearity error compensation for a reference input span up to 10 V |
 |5  |SDODIS  |0  |The SDO pin enabled for future readings from the part | |5  |SDODIS  |0  |The SDO pin enabled for future readings from the part |
 |4  |BIN/2sC  |1  |Offset binary coding | |4  |BIN/2sC  |1  |Offset binary coding |
-|[3:2]  |DACTRI, OPGND  |00  | Remove the DAC output clamp to ground  and place the DAC in normal operating mode | +|3  |DACTRI  |0  | Place the DAC in normal operating mode | 
-|1  |RBUF  | 1  |The internal amplifier powered down  | +|2  |OPGND  |0  | Remove the DAC output clamp to ground  | 
-</WRAP>   +|1  |RBUF  | 1  |Internal amplifier powered down  |
-\\ +
-\\+
  
-<WRAP important> +<WRAP center round important 60%> 
-To write in binary coding, select **BIN/2sC = 1**. +To write in offset binary coding, set BIN/2sC = 1. 
 \\ \\
 \\ \\
 The default coding is twos complement. The same 24-bit data impacts the values that the user writes to or reads from the part in a different way depending on the coding selected. The user must verify the coding used by writing to the control register or reading  back from it. The default coding is twos complement. The same 24-bit data impacts the values that the user writes to or reads from the part in a different way depending on the coding selected. The user must verify the coding used by writing to the control register or reading  back from it.
 </WRAP> </WRAP>
 +</WRAP>  
 \\ \\
 \\ \\
 +
 {{ :resources:quick-start:example1_step1_ad5781_91.png?direct&700 |}} {{ :resources:quick-start:example1_step1_ad5781_91.png?direct&700 |}}
 <WRAP CENTERALIGN>//Figure 6. Initializing the Part//</WRAP> <WRAP CENTERALIGN>//Figure 6. Initializing the Part//</WRAP>
Line 225: Line 220:
 === Writing to the DAC Register === === Writing to the DAC Register ===
 <WRAP tip>To write a midscale code to the DAC register,  <WRAP tip>To write a midscale code to the DAC register, 
-  * Set R/W = 0 to select the write option from the read/write bit. +  * Set R/<m>overline{W}</m> = 0 to select the write option from the read/write bit. 
   * Set C[2:0] = 001 for the correspondent register address.   * Set C[2:0] = 001 for the correspondent register address.
   * Set D[19:0], the data bits, for a midscale code.   * Set D[19:0], the data bits, for a midscale code.
- 
-See Table 7 and Figure 7.  
-\\ 
-\\ 
 The 24-bit data to write over the serial interface is as follows: The 24-bit data to write over the serial interface is as follows:
 \\ \\
Line 241: Line 232:
 \\ \\
 where X = don't care. where X = don't care.
 +\\
 +\\
 +See Table 7 and Figure 7. 
 \\ \\
 \\ \\
Line 247: Line 241:
 |23  |R/<m>overline{W}</m>  |0  |[[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] addressed for a write operation  | |23  |R/<m>overline{W}</m>  |0  |[[adi>ad5781|AD5781]]/[[adi>ad5791|AD5791]] addressed for a write operation  |
 |[22:20]  |C2, C1, C0  |001  |Write to the DAC register  | |[22:20]  |C2, C1, C0  |001  |Write to the DAC register  |
-|[19:0]  |D19 to D0  |1000 0000 0000 0000 00XX or 1000 0000 0000 0000 0000 |Midscale code  | 
 </WRAP> </WRAP>
 \\ \\
 {{ :resources:quick-start:example1_step2_ad5781_91.png?direct&700 |}} {{ :resources:quick-start:example1_step2_ad5781_91.png?direct&700 |}}
-<WRAP CENTERALIGN>//Figure 7. Write to the DAC Register//</WRAP>+<WRAP CENTERALIGN>//Figure 7. Writing to the DAC Register//</WRAP>
 \\ \\
  
Line 266: Line 259:
 \\ \\
 \\ \\
-18-bit **AD5781**: 0011 1111 1111 1111 1111 11XX+18-bit [[adi>ad5781|AD5781]]: 0011 1111 1111 1111 1111 11XX 
 +\\ 
 +20-bit [[adi>ad5791|AD5791]]: 0011 1111 1111 1111 1111 1111 
 +\\ 
 +\\ 
 +where X = don't care.  
 +\\ 
 +\\ 
 +See Figure 8.
 \\ \\
-20-bit **AD5791**: 0011 1111 1111 1111 1111 1111 
 \\ \\
 </WRAP> </WRAP>
Line 278: Line 278:
 \\ \\
 === Writing to the Software Control Register === === Writing to the Software Control Register ===
-<WRAP tip>Set the CLR bit to a Logic 1 to set the DAC register to a user defined value and update the DAC output. \\ +<WRAP tip>Set the CLR bit to a Logic 1 to set the DAC register to a user defined value and update the DAC output. 
-\\ +
-See Figure 9.+
 \\ \\
 \\ \\
Line 287: Line 285:
 \\ \\
 The user should see the DAC output value change to full-scale code. The user should see the DAC output value change to full-scale code.
 +\\
 +\\
 +See Figure 9.
 </WRAP> </WRAP>
 \\ \\
Line 294: Line 295:
 \\ \\
 \\ \\
-=== Reading Back the Clearcode Register === +=== Reading From the Clearcode Register === 
-<WRAP tip>To confirm the clearcode value written to the part, read the data on the clearcode register (Full scale for this example). Write the following over the serial interface: 1011 XXXX XXXX XXXX XXXX XXXX.+<WRAP tip>To confirm the clearcode value written to the part, read the data from the clearcode register (full scale for this example).  
 +\\ 
 +\\ 
 +Write the following over the serial interface:  
 +\\ 
 +\\ 
 +1011 XXXX XXXX XXXX XXXX XXXX 
 +\\ 
 +\\ 
 +where X = don't care. 
 +\\ 
 +\\ 
 +See Figure 10. 
 +\\ 
 +\\
 <WRAP center round important 60%> <WRAP center round important 60%>
-Remember that this action is a read function, so the R/<m>overline{W}</m> bit is set to **"1"**.+Note that this action is a read function. Therefore, set the R/<m>overline{W}</m> bit = 1.
 \\ \\
 \\ \\
-The data bits are **don't care**, as the aim is to read from the part and not a write function.+D19 to D0, the data bits, are don't care bits because the intention is to read from the part, and not to write to the part.
 </WRAP> </WRAP>
  
Line 307: Line 322:
 \\ \\
 {{ :resources:quick-start:example2_step3_ad5781_91.png?direct&700 |}} {{ :resources:quick-start:example2_step3_ad5781_91.png?direct&700 |}}
-<WRAP CENTERALIGN>//Figure 10. Readback from the clearcode register//</WRAP>+<WRAP CENTERALIGN>//Figure 10. Reading from the Clearcode Register//</WRAP>
 \\ \\
resources/quick-start/ad5791.1365698496.txt.gz · Last modified: 11 Apr 2013 18:41 by Yuet Ng

Page Tools