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- 03_analyis.png
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- 10 Nov 2022 04:10
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- 04_waveform.png
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- 10 Nov 2022 04:10
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- 10 Nov 2022 04:22
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- ace_schematic_borderless_page_1.png
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- 04 Nov 2022 03:39
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- 04 Nov 2022 04:21
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- adaq7768-1_evb.png
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- 03 May 2023 13:56
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- ev-adaq7768-1fmc1ztop.jpg
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- 28 Jul 2022 10:18
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- 19 Jul 2022 05:35
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- fig_7_choose_install_location.png
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- fig_12_checking_that_the_evb_is_connected_to_the_pc_correctly.png
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- 26 Aug 2022 04:54
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- fig_13_ev-adaq7768-1fmc1z_ace_software_main_window.png
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- 19 Jul 2022 08:58
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- fig_13_ev-adaq7768-1fmc1z_ace_software_main_window_new.png
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- fig_14_ev-adaq7768-1fmc1z_board_view.png
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- 21 Jul 2022 04:33
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- fig_20_input_range_mode_selection.png
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- fig_22_fft_plot_for_a_typical_ac_measurement.png
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- 19 Jul 2022 05:35
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- fig_24_set_the_sinc3_filter_decimation_ratio.png
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- fig_25_sinc3_filter_decimation_ratio_using_memory_map_view.png
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- fig_26_change_the_number_of_samples_to_collect_per_sample_run.png
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- fig_26_change_the_number_of_samples_to_collect_per_sample_run_new.png
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- 30 Aug 2022 04:56
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- fig_27_fft_plot_for_a_typical_dc_measurement_with_gain6_mode_input_shorted_odr_50sps_1024_samples.png
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- 19 Jul 2022 05:35
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- fig_27_fft_plot_for_a_typical_dc_measurement_with_gain6_mode_input_shorted_odr_50sps_1024_samples_new.png
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- 30 Aug 2022 04:56
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- fig_28_histogram.png
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- fig_29_histogram_sinc3.png
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- fig_32_fft_plot_for_a_typical_dc_measurement_with_gain2_mode_input_shorted_odr_50sps_1024_samples.png
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- 06 Sep 2022 05:17
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- fig_33_histogram_for_a_typical_dc_measurement_with_gain2_mode_input_shorted_odr_50sps_1024_samples.png
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- 06 Sep 2022 05:17
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- Date:
- 19 Jul 2022 03:26
- Filename:
- fig_20_input_range_mode_selection.png
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resources/fpga/xilinx/interposer/common_sdp.txt · Last modified: 28 Sep 2012 10:32 by Adrian Costina