The most recent version of this page is a draft.
This version (04 Nov 2022 04:30) was approved by Chelsea Faye Aure.The Previously approved version (08 Sep 2022 04:47) is available.
This version (04 Nov 2022 04:30) was approved by Chelsea Faye Aure.The Previously approved version (08 Sep 2022 04:47) is available.This is an old revision of the document!
Table of Contents
Evaluating the ADAQ7768-1 24-Bit, Single Channel Precision μModule® Data Acquisition System
Features
- Evaluation kit for ADAQ7768-1 24-Bit Single Channel Precision μModule® Data Acquisition System
- Switch or GPIO controlled gain mode
- Complete power management solution
- FMC connector to FPGA for digital interface
- Optional Arduino and PMOD connector
Evaluation Kit Contents
- EV-ADAQ7768-1FMC1Z evaluation board
Equipment Needed
- SDP-H1 (EVAL-SDP-CH1Z) system demonstration platform
- DC/AC signal source (Audio Precision or similar high performance signal source)
- PC running Windows 7, Windows 8, or Windows 10 with USB 2.0 port
Software Requirement
- ACE (Analysis, Control, Evaluation) software.
General Description
The EV-ADAQ7768-1FMC1Z evaluation kit features the ADAQ7768-1 24-bit, single channel precision μModule® data acquisition System. The EV-ADAQ7768-1FMC1Z board connects to the USB port of the PC via the SDP-H1 motherboard. By default, power is supplied from the SDP-H1 supply, which is scaled to ±15V, 5.3V and 3.3 V to supply the ADAQ7768-1 and support components. The EV-ADAQ7768-1FMC1Z software fully configures the ADAQ7768-1 device register functionality and provides DC and AC time and frequency domain analysis in the form of waveform graphs, histograms, and associated noise analysis for ADC performance evaluation. The EV-ADAQ7768-1FMC1Z is an evaluation board that allows the user to evaluate the features of the ADAQ7768-1 μModule®. The user PC software executable controls the EV-ADAQ7768-1FMC1Z over USB through the system demonstration platform (SDP-H1).
Evaluation Board Photograph
Figure 1. Board Photo
Quick Start Guide
To begin using the evaluation board, take the following steps:
- Ensure the SDP-H1 system demonstration platform board is disconnected from the PC. Install the ACE (Analysis, Control, Evaluation) software to evaluate ADAQ7768-1. Restart the PC after the software installation is complete. For complete software installation instructions, see the Software Installation Procedures section.
- Connect the SDP-H1 system demonstration platform board to the unpowered EV-ADAQ7768-1FMC1Z evaluation board. The J4 connector of the SDP-H1 system demonstration platform board connects to the receiving socket, P1, on the EV-ADAQ7768-1FMC1Z printed circuit board (PCB).
- Ensure the evaluation boards are connected firmly together by screwing them together.
- Connect the 12V DC supply to the SDP-H1 system demonstration platform board and then connect to the PC using the supplied USB cable. Choose to automatically search for the drivers for the SDP-H1 if prompted by the operating system.
- Launch the ACE (Analysis, Control, Evaluation) software from the Analog Devices subfolder in the Programs menu.
To power off, first close the software. Then press the reset button on the SDP-H1 before disconnecting the power or USB.
Design Overview
Figure 2. Functional Block Diagram
Evaluation Board Hardware
Hardware Link Options
Table 1. Default Link and Solder Link Options
| Name | Link No. | Default Link Option | Description |
|---|---|---|---|
| Differential/Single Ended Input | R53 R54 | DNI | R53 set IN+ to ground for single ended input R54 set IN- to ground for single ended input |
| ADR4540 Vin Select | R23 R60 | R23 | Set the source for the voltage input for ADR4540 R23 set ADR4540 voltage input to the output of the LDO R60 set ADR4540 voltage input to 5.3V |
| FDA Power Mode Input | R10 R11 | DNI | Set the power mode selection to auto or manual selection R10 set the M1_FDA power mode input to manual selection R11 set the M0_FDA power mode input to manual selection |
| S2 | 1A-1B 2A-2B 3A-3B 4A-4B 5A-5B | | Set the GPIO mode and FDA power mode 1A-1B set the GPIO0 to high or low 2A-2B set the GPIO1 to high or low 3A-3B set the GPIO2 to high or low 4A-4B set the M1_FDA power mode to low power mode or high power mode 5A-5B set the M0_FDA power mode to low power mode or high power mode |
On-Board Connectors
Table 2 provides information about the external on-board connectors on the EV-ADAQ7768-1FMC1Z.
Table 2. On-Board Connectors
| Connector | Function |
|---|---|
| P1 | Connects all digital signals to the SDP-H1 board |
| P2/P3 | Arduino header pads, not installed by default |
| P5 | PMOD connector block |
| P14 | DC analog inputs |
| J3/J4/P7 | SMB and Terminal Block connector for analog inputs, IN+, IN- |
| S1 | ADC reset switch |
| S2 | Mechanical switch for Gain and FDA power mode control |
| J1 | SMB connector for the external MCLK |
| J2 | SMB connector for the low voltage differential signaling (LVDS) clock on the XTAL1 pin |
Power Supplies
The evaluation board requires 3.3V power supply to operate. By default, the 3.3V rail is supplied by the SDP-H1, and the SDP-H1 is powered by a 12V wall adapter. The terminal block P14, can also be used to supply the evaluation board with 3.3V in case the user prefers to evaluate the EV-ADAQ7768-1FMC1Z with a third-party capture board.
The EV-ADAQ7768-1FMC1Z uses LT3095 (U2), a dual channel integrated boost and LDO regulator in a single package. LT3095 generates the +15V needed by the VDD_PGA pin of ADAQ7768-1 and a 5.3V to supply the built-in LDO of ADAQ7768-1. The LDO of the ADAQ7768-1 is used to power the VDD2_PGA, VDD_FDA, VDD_ADC, VDD2_ADC, and the ADR4540 reference device as shown on ADAQ7768-1 Datasheet Quick Start Up Guide.
ADP2300 (U1) is used to scale the 3.3V from SDP-H1 to -16V, while ADP7182 (U3) — a low noise LDO, regulates the voltage to -15V which is used by the VSS_PGA.
The 3.3V from SDP-H1 is also used to supply the power needed on the VDD_IO.
Evaluation Board Setup Procedures
After following the instructions in the Software Installation Procedure section, set up the evaluation and SDP board as detailed in this section.
Setup Requirement
Hardware Requirement
- EV-ADAQ7768-1FMC1Z
- SDP-H1 digital interfacing board
Software Requirement
ADAQ7768-1 customer evaluation software tool
Figure 3. Board Connection
Board Connection
Follow the board connection shown in Figure 4. Connect the SDP-H1 with the 12V wall adapter and to PC through a USB cable.
Startup Sequence
After running the software, the following sequence of event occurs:
- The software accesses the EPPROM on the main evaluation board, which contains the board ID
- Once the EEPROM value is verified, the PC loads the corresponding firmware to the FPGA on the SDP-H1.
- After the loading of the firmware, the SDP-H1 supplies the 3.3V to the main evaluation board and establishes communication with the DUT.
- The software then loads a preset of register values to the DUT’s user register map to configure the DUT to the tool’s default operating mode.
Warning
The ACE software and drivers must be installed before connecting the evaluation board and the SDP-H1 to the USB port of the PC to ensure the evaluation system is correctly recognized when it is connected to the PC.
Configuring the Evaluation and SDP Board
Connect the SDP-H1 to P1 on the EV-AD7768-1FMCZ board. Screw the two boards together.
Evaluation Board Software
Software Installation Procedures
Before using the EV-ADAQ7768-1FMC1Z, download and install the ACE (Analysis, Control, Evaluation) software.
ACE is a desktop software application allowing the evaluation and control of multiple evaluation systems across the Analog Devices product portfolio. The installation process consists of the ACE Software Installation and the SDP-H1 driver installation.
To ensure that the evaluation system is correctly recognized when it is connected to the PC, install the ACE software and the SDP-H1 driver before connecting the EV-ADAQ7768-1FMC1Z and the SDP-H1 board to the USB port of the PC.
Figure 5. Evaluation Software Install Confirmation
Figure 6. License Agreement
Figure 7. Choose Install Location
Figure 8. Choose Components
Figure 9. Windows Security Window
Figure 10. Installation in Progress
Figure 11. Installation Complete
Setting Up the System for Data Capture
After completing the steps in the Evaluation Board Software section and the Evaluation Board Hardware section, set up the system for data capture as follows:
- Run the Found New Hardware Wizard after the SDP-H1 system demonstration platform board is plugged into the PC. If using Windows XP, the user may need to search for the SDP-H1 drivers. Automatically search for the drivers for the SDP-H1 system demonstration platform board if prompted by the operating system.
- Check that the evaluation board is connecting to the PC correctly using the Device Manager of the PC. Access the Device Manager as follows:
- Right click My Computer and then click Manage.
- A dialog box appears asking for permission to allow the program to make changes to the computer. Click Yes.
- The Computer Management window appears. Click Device Manager from the list of System Tools (see Figure 4).
- If the SDP-H1 system demonstration platform board appears under ADI Development Tools, the driver software is installed and the evaluation board is connecting to the PC correctly.
Figure 4. Checking that the Evaluation Board is connected to the PC correctly
Launching the Software
When the EV-ADAQ7768-1FMC1Z and SDP-H1 boards are properly connected to the PC, launch the ACE software. To launch the ACE software, take the following steps:
- From the Start menu, select All Programs > Analog Devices > ACE > ACE.exe to open the main software window shown in Figure 5.
Figure 5. EV-ADAQ7768-1FMC1Z ACE Software Main Window
- The EV-ADAQ7768-1FMC1Z icon appears in the Attached Hardware section.
- If the EV-ADAQ7768-1FMC1Z is not connected to the USB port via the SDP-H1 board when the software is launched, the EV-ADAQ7768-1FMC1Z board icon does not appear in the Attached Hardware section. Connect the EV-ADAQ7768-1FMC1Z and SDP-H1 board to the USB port of the PC and wait a few seconds, then continue following these instructions.
- Double-click the EV-ADAQ7768-1FMC1Z board icon to open the window shown in Figure 6.
Figure 6. EV-ADAQ7768-1FMC1Z Board View
- Double-click the EV-ADAQ7768-1FMC1Z chip icon to open the window shown in Figure 7.
Figure 7. EV-ADAQ7768-1FMC1Z Chip View
- Click Software Defaults and then click Apply Changes.
- Click Proceed to Analysis to open the EV-ADAQ7768-1FMC1Z analysis shown in Figure 8.
Description of the Analysis Window
Click Proceed to Analysis in the chip view window to open the window shown in Figure 7. The analysis view contains the Waveform tab, the Histogram tab, and the FFT tab.
Capture Settings
- ODR (Output Data Rate). The ODR is automatically calculated by the software based on the selected ADC filter settings. By default, this is set to 256 kSPS.
- Sample Count. The default sample count is set at 8192 samples, but it can be changed to the selection of the dropdown list, ranging from 512 to 131072 samples.
Click Run Once in the Capture Settings section to start a data capture of the samples at the sample rate specified in the Sample Count dropdown list. These samples are stored on the FPGA device and are only transferred to the PC when the sample frame is complete.
Click Run Continuously in the Capture Settings section to start a data capture that gathers samples continuously with one batch of data at a time.
Waveform Tab
The Waveform Results section displays time domain characteristics of the signal, such as minimum, maximum, and peak-to-peak expressed in codes or in volts.
The data waveform graph shows each successive sample of the µModule output. The user can zoom in on and pan across the waveform using the embedded waveform tools. The channels to display can be selected in the Display Channels section.
Click the display unit’s dropdown list (shown with the Volts option selected in Figure 8) to select whether the data graph displays in units of hexadecimal, volts, or codes.
The axis controls are dynamic. When selecting either y-scale dynamic or x-scale dynamic, the corresponding axis width automatically adjusts to show the entire range of the µModule results after each batch of samples.
Figure 8. EV-ADAQ7768-1FMC1Z Waveform
Histogram Tab
The Histogram tab contains the histogram graph, together with the capture results related to the dc performance (as shown in Figure 9).
The histogram graph displays the number of hits per code within the sampled data. This graph is useful for dc analysis and indicates the noise performance of the device.
Figure 9. EV-ADAQ7768-1FMC1Z Histogram
FFT Tab
The FFT tab displays a frequency domain graph of the last batch of samples gathered, as shown in Figure 10 and Figure 11. Controls above the graph allow zooming and panning and control over amplitude and frequency scaling. Other noise parameters are also shown beside the graph.
Figure 10. EV-ADAQ7768-1FMC1Z FFT
Figure 11. EV-ADAQ7768-1FMC1Z FFT (with shorted inputs)
Exporting Data
Click Export to export captured data. The waveform, histogram, and FFT data is stored in .xml files along with the values of parameters at capture.
Configuring the Board and DUT
Input Range Control
There are two ways to control the DUT input range.
- Through the GPIO of the DUT, controlled over the SPI interface.
- Through on-board mechanical switch S2.
By default, the ACE software uses the GPIO to control the input range. The user can configure the PGIA gain by clicking the PGIA icon in the Chip View of the ACE software to select the input ranges. Once done, the user must click Apply Changes located at the upper left corner in order for the PGIA gain to take effect.
The user needs to set S2 switches to LO in order to properly control the device input range using GPIO.
Figure 12. Input range selection menu
Alternatively, the user can choose to select the input range through an onboard mechanical switch S2. For this to work, check the Control PGIA with switch in the PGIA Gain section. Then, click the Apply Changes for this to take effect.
Figure 13. Input range mode selection
The user can then control the input range setting using switch S2, see Table 3 for more details. Note, when choosing the manual input range control option, the user is responsible of adjusting the Gain Mode Setting in the software accordingly in order for the software to display the correct measurement result.
Table 3. Configuration Switch S2 Functions
| Name | Description |
|---|---|
| GAIN0, GAIN1, GAIN2 (labelled as A0, A1, A2 on Rev. A board) | Gain mode/input range control for the ADAQ7768-1. (See Table 4 for more details.) Set to LO for GPIO input control mode. |
| FDA_M0 | Reserved. Default low. |
| FDA_M1 | Reserved. Default low. |
Table 4. PGIA Mode Settings
| Gain Setting | Differential Input Range (V) | GAIN2 | GAIN1 | GAIN0 |
|---|---|---|---|---|
| Shut Down | H | H | H | |
| Gain0 | ±12.603 | H | H | L |
| Gain1 | ±6.302 | H | L | H |
| Gain2 | ±3.151 | H | L | L |
| Gain3 | ±1.575 | L | H | H |
| Gain4 | ±0.788 | L | H | L |
| Gain5 | ±0.394 | L | L | H |
| Gain6 | ±0.197 | L | L | L |
Input Configuration
Provide the input signal through screw terminal or the SMB connectors.
The default board inputs are floating with high impedance. The user needs to ensure the source signal is properly biased to a common mode voltage.
The true dynamic range of the board can be measured by connect the two inputs to the board’s ground reference through the screw terminal by a short piece of wire.
Figure 14. Short the inputs to ground with wire to measure the signal chain dynamic range
The ADAQ7768-1 has excellent performance in both AC and DC measurement. The digital filter inside the ADAQ7768-1 can be programmed with a wide range of decimation ratios to achieve input bandwidth from a few Hertz to a maximum of 204kHz.
AC Measurement
By default, the software configures the DUT to perform wide bandwidth measurement with the wideband low ripple digital filter (brick wall) of 110kHz of -3dB BW.
In this mode the user can evaluate the wide band dynamic range (noise) as well as other AC performances such as SNR, THD and SFDR etc.
The user can also test the device’s anti-aliasing performance by sweeping an out of band signal to the input across frequency.
Figure 15. FFT plot for a typical AC measurement
DC Measurement
A Sinc3 filter with ODR=50SPS is a sweet spot for the measurement of a pure DC signal. As the Sinc notch appears at 50Hz and can be used to reject the 50Hz line frequency. Take the following steps to setup the DUT for a 50SPS Sinc3 filter:
- As an example for RMS noise, short IN- and IN+ connectors to ground.
- At the Chip View of the ACE software, click the Filter Configuration icon.
- Use the drop-down menu to select Sinc3 (programmable decimation rate) option as shown in Figure 16.
- Configure the Sinc3 Decimation Rate by typing in the value ‘13FF’ in the text box near the lower right corner as shown in Figure 17. This is also reflected in the registers SINC3_DEC_RATE_LSB and SINC3_DEC_ RATE_MSB located at the memory map of the ACE software (see Figure 18). Afterwards, click Apply Changes for this to take effect.
Figure 16. Set the digital filter type.
Figure 17. Set the Sinc3 filter decimation ratio.
Figure 18. Sinc3 filter decimation ratio using Memory Map View.
- Before clicking on the Run Once button, make sure to adjust the number of samples to be collected accordingly.
Figure 19. Change the number of samples to collect per sample run
- Collecting the default 8192 samples at 50SPS will take 8192*1/50/60=2.73 minutes! Start with 1024 samples, which should take about 20 seconds. Generate new capture using 1024 samples.
Figure 20. FFT plot for a typical DC measurement, with Gain6 mode, input shorted, ODR=50sps, 1024 samples.
- The same condition (Sinc3 50SPS) is used to measure Low Frequency Noise, as specified in the datasheet. In the Histogram tab, noise is displayed as Transition noise in LSB. To compare with datasheet’s referred to input (RTI) Low Frequency Noise in μVrms, apply the formula:
- For example, using Gain2 Mode (AFE_GAIN = 1.3 V/V) with measured Transition Noise = 1.508 LSB = 0.566 μVrms RTI.
Figure 21. Histogram of output codes. with Gain2 mode, input shorted, ODR=50sps, 1024 samples.
Calculating SINC3_DEC_RATE Value
For a 16.384 MHz MCLK to achieve an ODR of 50 Hz using the Sinc3 filter, use the following equation and determine the DEC_RATE:
With the ADAQ7768-1 MCLK_DIV = 2,
To program the Sinc3 decimation ratio, the user must first calculate for the equivalent Sinc3 decimation ratio to be written on SINC3_DECIMATION_RATE registers (SINC3_DEC_RATE_MSB and SINC3_DEC_RATE_LSB) using the equation below:
To set the decimation ration to 163,840, write the equivalent hexadecimal value of 5119 to SINC3_DEC_RATE_MSB and SINC3_DEC_RATE_LSB registers because the value in the register is incremented by 1 and then multiplied by 32 to give the actual decimation rate.
Refer to the ADAQ7768-1 datasheet for more information on the DUT register configuration.
Exiting the Software
To exit the software, click file icon on the upper right tab and then click Exit.
Reset Switches
Press S1 switch to reset the DUT. Resetting the DUT will reset all the register settings to its default value.
A reset switch is also available on the SDP-H1 to reset the interface board. Resetting the digital interface board will result in losing communication with the DUT.
The user can restart the software tool to re-initialize the board.
Evaluation Board Schematic
Figure 22. EV-ADAQ7768-1FMC1Z Board Schematic Page 1
Figure 23. EV-ADAQ7768-1FMC1Z Board Schematic Page 2
/srv/wiki.analog.com/data/pages/resources/eval/user-guide/adaq7768-1-eval-board.txt · Last modified: 03 May 2023 14:02 by Chelsea Faye Aure