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The EV-ADAQ7768-1FMC1Z evaluation kit features the ADAQ7768-1 24-bit, single channel precision μModule® data acquisition System. The EV-ADAQ7768-1FMC1Z board connects to the USB port of the PC via the SDP-H1 motherboard. By default, power is supplied from the SDP-H1 supply, which is scaled to ±15V, 5.3V and 3.3 V to supply the ADAQ7768-1 and support components. The EV-ADAQ7768-1FMC1Z software fully configures the ADAQ7768-1 device register functionality and provides DC and AC time and frequency domain analysis in the form of waveform graphs, histograms, and associated noise analysis for ADC performance evaluation. The EV-ADAQ7768-1FMC1Z is an evaluation board that allows the user to evaluate the features of the ADAQ7768-1 μModule®. The user PC software executable controls the EV-ADAQ7768-1FMC1Z over USB through the system demonstration platform (SDP-H1).
Figure 1. Board Photo
To begin using the evaluation board, take the following steps:
To power off, first close the software. Then press the reset button on the SDP-H1 before disconnecting the power or USB.
Figure 2. Functional Block Diagram
Table 1. Default Link and Solder Link Options
|Name||Link No.||Default Link Option||Description|
| Differential/Single Ended Input || |
| DNI ||
R53 set IN+ to ground for single ended input
R54 set IN- to ground for single ended input
| ADR4540 Vin Select || |
| R23 ||
Set the source for the voltage input for ADR4540
R23 set ADR4540 voltage input to the output of the LDO
R60 set ADR4540 voltage input to 5.3V
| FDA Power Mode Input || |
| DNI ||
Set the power mode selection to auto or manual selection
R10 set the M1_FDA power mode input to manual selection
R11 set the M0_FDA power mode input to manual selection
| S2 || |
Set the GPIO mode and FDA power mode
1A-1B set the GPIO0 to high or low
2A-2B set the GPIO1 to high or low
3A-3B set the GPIO2 to high or low
4A-4B set the M1_FDA power mode to low power mode or high power mode
5A-5B set the M0_FDA power mode to low power mode or high power mode
Table 2 provides information about the external on-board connectors on the EV-ADAQ7768-1FMC1Z.
Table 2. On-Board Connectors
|P1||Connects all digital signals to the SDP-H1 board|
|P2/P3||Arduino header pads, not installed by default|
|P5||PMOD connector block|
|P14||DC analog inputs|
|J3/J4/P7||SMB and Terminal Block connector for analog inputs, IN+, IN-|
|S1||ADC reset switch|
|S2||Mechanical switch for Gain and FDA power mode control|
|J1||SMB connector for the external MCLK|
|J2||SMB connector for the low voltage differential signaling (LVDS) clock on the XTAL1 pin|
The evaluation board requires 3.3V power supply to operate. By default, the 3.3V rail is supplied by the SDP-H1, and the SDP-H1 is powered by a 12V wall adapter. The terminal block P14, can also be used to supply the evaluation board with 3.3V in case the user prefers to evaluate the EV-ADAQ7768-1FMC1Z with a third-party capture board.
The EV-ADAQ7768-1FMC1Z uses LT3095 (U2), a dual channel integrated boost and LDO regulator in a single package. LT3095 generates the +15V needed by the VDD_PGA pin of ADAQ7768-1 and a 5.3V to supply the built-in LDO of ADAQ7768-1. The LDO of the ADAQ7768-1 is used to power the VDD2_PGA, VDD_FDA, VDD_ADC, VDD2_ADC, and the ADR4540 reference device as shown on ADAQ7768-1 Datasheet Quick Start Up Guide.
ADP2300 (U1) is used to scale the 3.3V from SDP-H1 to -16V, while ADP7182 (U3) — a low noise LDO, regulates the voltage to -15V which is used by the VSS_PGA.
The 3.3V from SDP-H1 is also used to supply the power needed on the VDD_IO.
After following the instructions in the Software Installation Procedure section, set up the evaluation and SDP board as detailed in this section.
ADAQ7768-1 customer evaluation software tool
Figure 3. Board Connection
Follow the board connection shown in Figure 4. Connect the SDP-H1 with the 12V wall adapter and to PC through a USB cable.
After running the software, the following sequence of event occurs:
Connect the SDP-H1 to P1 on the EV-AD7768-1FMCZ board. Screw the two boards together.
Before using the EV-ADAQ7768-1FMC1Z, download and install the ACE (Analysis, Control, Evaluation) software.
ACE is a desktop software application allowing the evaluation and control of multiple evaluation systems across the Analog Devices product portfolio. The installation process consists of the ACE Software Installation and the SDP-H1 driver installation.
To ensure that the evaluation system is correctly recognized when it is connected to the PC, install the ACE software and the SDP-H1 driver before connecting the EV-ADAQ7768-1FMC1Z and the SDP-H1 board to the USB port of the PC.
After completing the steps in the Evaluation Board Software section and the Evaluation Board Hardware section, set up the system for data capture as follows:
When the EV-ADAQ7768-1FMC1Z and SDP-H1 boards are properly connected to the PC, launch the ACE software. To launch the ACE software, take the following steps:
Figure 5. EV-ADAQ7768-1FMC1Z ACE Software Main Window
Figure 6. EV-ADAQ7768-1FMC1Z Board View
Figure 7. EV-ADAQ7768-1FMC1Z Chip View
Click Proceed to Analysis in the chip view window to open the window shown in Figure 7. The analysis view contains the Waveform tab, the Histogram tab, and the FFT tab.
Click Run Once in the Capture Settings section to start a data capture of the samples at the sample rate specified in the Sample Count dropdown list. These samples are stored on the FPGA device and are only transferred to the PC when the sample frame is complete.
Click Run Continuously in the Capture Settings section to start a data capture that gathers samples continuously with one batch of data at a time.
The Waveform Results section displays time domain characteristics of the signal, such as minimum, maximum, and peak-to-peak expressed in codes or in volts.
The data waveform graph shows each successive sample of the µModule output. The user can zoom in on and pan across the waveform using the embedded waveform tools. The channels to display can be selected in the Display Channels section.
Click the display unit’s dropdown list (shown with the Volts option selected in Figure 8) to select whether the data graph displays in units of hexadecimal, volts, or codes.
The axis controls are dynamic. When selecting either y-scale dynamic or x-scale dynamic, the corresponding axis width automatically adjusts to show the entire range of the µModule results after each batch of samples.
Figure 8. EV-ADAQ7768-1FMC1Z Waveform
The Histogram tab contains the histogram graph, together with the capture results related to the dc performance (as shown in Figure 9).
The histogram graph displays the number of hits per code within the sampled data. This graph is useful for dc analysis and indicates the noise performance of the device.
Figure 9. EV-ADAQ7768-1FMC1Z Histogram
The FFT tab displays a frequency domain graph of the last batch of samples gathered, as shown in Figure 10 and Figure 11. Controls above the graph allow zooming and panning and control over amplitude and frequency scaling. Other noise parameters are also shown beside the graph.
Figure 10. EV-ADAQ7768-1FMC1Z FFT
Figure 11. EV-ADAQ7768-1FMC1Z FFT (with shorted inputs)
Click Export to export captured data. The waveform, histogram, and FFT data is stored in .xml files along with the values of parameters at capture.
There are two ways to control the DUT input range.
By default, the ACE software uses the GPIO to control the input range. The user can configure the PGIA gain by clicking the PGIA icon in the Chip View of the ACE software to select the input ranges. Once done, the user must click Apply Changes located at the upper left corner in order for the PGIA gain to take effect.
The user needs to set S2 switches to LO in order to properly control the device input range using GPIO.
Figure 12. Input range selection menu
Alternatively, the user can choose to select the input range through an onboard mechanical switch S2. For this to work, check the Control PGIA with switch in the PGIA Gain section. Then, click the Apply Changes for this to take effect.
Figure 13. Input range mode selection
The user can then control the input range setting using switch S2, see Table 3 for more details. Note, when choosing the manual input range control option, the user is responsible of adjusting the Gain Mode Setting in the software accordingly in order for the software to display the correct measurement result.
Table 3. Configuration Switch S2 Functions
A0, A1, A2 on
Rev. A board)
| Gain mode/input range control for the ADAQ7768-1.
(See Table 4 for more details.)
Set to LO for GPIO input control mode.
|FDA_M0||Reserved. Default low.|
|FDA_M1||Reserved. Default low.|
Table 4. PGIA Mode Settings
|Gain Setting||Differential Input Range (V)||GAIN2||GAIN1||GAIN0|
Provide the input signal through screw terminal or the SMB connectors.
The default board inputs are floating with high impedance. The user needs to ensure the source signal is properly biased to a common mode voltage.
The true dynamic range of the board can be measured by connect the two inputs to the board’s ground reference through the screw terminal by a short piece of wire.
Figure 14. Short the inputs to ground with wire to measure the signal chain dynamic range
The ADAQ7768-1 has excellent performance in both AC and DC measurement. The digital filter inside the ADAQ7768-1 can be programmed with a wide range of decimation ratios to achieve input bandwidth from a few Hertz to a maximum of 204kHz.
By default, the software configures the DUT to perform wide bandwidth measurement with the wideband low ripple digital filter (brick wall) of 110kHz of -3dB BW.
In this mode the user can evaluate the wide band dynamic range (noise) as well as other AC performances such as SNR, THD and SFDR etc.
The user can also test the device’s anti-aliasing performance by sweeping an out of band signal to the input across frequency.
Figure 15. FFT plot for a typical AC measurement
A Sinc3 filter with ODR=50SPS is a sweet spot for the measurement of a pure DC signal. As the Sinc notch appears at 50Hz and can be used to reject the 50Hz line frequency. Take the following steps to setup the DUT for a 50SPS Sinc3 filter:
Figure 16. Set the digital filter type.
Figure 17. Set the Sinc3 filter decimation ratio.
Figure 18. Sinc3 filter decimation ratio using Memory Map View.
Figure 19. Change the number of samples to collect per sample run
Figure 20. FFT plot for a typical DC measurement, with Gain6 mode, input shorted, ODR=50sps, 1024 samples.
Figure 21. Histogram of output codes. with Gain2 mode, input shorted, ODR=50sps, 1024 samples.
For a 16.384 MHz MCLK to achieve an ODR of 50 Hz using the Sinc3 filter, use the following equation and determine the DEC_RATE:
With the ADAQ7768-1 MCLK_DIV = 2,
To program the Sinc3 decimation ratio, the user must first calculate for the equivalent Sinc3 decimation ratio to be written on SINC3_DECIMATION_RATE registers (SINC3_DEC_RATE_MSB and SINC3_DEC_RATE_LSB) using the equation below:
To set the decimation ration to 163,840, write the equivalent hexadecimal value of 5119 to SINC3_DEC_RATE_MSB and SINC3_DEC_RATE_LSB registers because the value in the register is incremented by 1 and then multiplied by 32 to give the actual decimation rate.
Refer to the ADAQ7768-1 datasheet for more information on the DUT register configuration.
To exit the software, click file icon on the upper right tab and then click Exit.
Press S1 switch to reset the DUT. Resetting the DUT will reset all the register settings to its default value.
A reset switch is also available on the SDP-H1 to reset the interface board. Resetting the digital interface board will result in losing communication with the DUT.
The user can restart the software tool to re-initialize the board.
Figure 22. EV-ADAQ7768-1FMC1Z Board Schematic Page 1
Figure 23. EV-ADAQ7768-1FMC1Z Board Schematic Page 2