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- 2channel_cpack_1.svg
- 19 Jun 2017 11:09
- 46.6 KB
- 2channel_upack_4.svg
- 06 Apr 2017 15:33
- 48.3 KB
- 3channel_cpack_1.svg
- 19 Jun 2017 11:09
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- 3channel_upack_4.svg
- 06 Apr 2017 15:33
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- 4channel_cpack_1.svg
- 19 Jun 2017 11:09
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- 4channel_upack_4.svg
- 06 Apr 2017 15:33
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- 7s_encoding_clocking.jpg
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- 19 Feb 2019 14:15
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- 7s_wizard_encoding_clocking.jpg
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- 19 Feb 2019 14:17
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- 7s_wizard_init.jpg
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- 19 Feb 2019 16:36
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- 7s_wizard_linerate.jpg
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- 19 Feb 2019 14:13
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- ad353xr_hdl_bd.svg
- 20 Mar 2023 08:42
- 21.3 KB
- ad463x_echo_hdl.svg
- 02 Feb 2021 13:30
- 104.8 KB
- ad463x_hdl.svg
- 02 Feb 2021 12:46
- 98.8 KB
- ad463x_hdl_cm0_cz1.svg
- 18 Oct 2021 22:06
- 103.6 KB
- ad463x_hdl_cm0_cz1_0.svg
- 18 Oct 2021 22:21
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- ad463x_hdl_cm0_cz1_1.svg
- 03 Feb 2022 15:18
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- ad463x_hdl_cm0_cz2.svg
- 18 Oct 2021 22:06
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- ad463x_hdl_cm0_cz2_0.svg
- 18 Oct 2021 23:06
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- ad463x_hdl_cm0_cz2_1.svg
- 18 Oct 2021 23:20
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- ad463x_hdl_cm1_cz2.svg
- 18 Oct 2021 22:06
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- ad463x_hdl_cm1_cz2_1.svg
- 03 Feb 2022 15:22
- 108.3 KB
- ad469x_hdl.svg
- 20 Oct 2020 16:33
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- ad469x_hdl1.svg
- 20 Oct 2020 16:34
- 92.5 KB
- ad713x_data_interface.svg
- 22 Mar 2018 16:35
- 29.2 KB
- ad713x_hdl_2.svg
- 11 Feb 2022 16:51
- 97.1 KB
- ad713x_hdl_3.svg
- 13 Apr 2022 10:38
- 98.2 KB
- ad9083_evb_2.svg
- 09 Mar 2021 16:16
- 82.9 KB
- ad9671.svg
- 02 Mar 2017 13:50
- 56.1 KB
- ad9684.svg
- 01 Mar 2017 09:23
- 49.1 KB
- ad9695_eval_setup.jpg
- 4000×3000
- 21 Jan 2021 10:30
- 4.1 MB
- ad9695_fmc.svg
- 07 Apr 2022 16:02
- 80.3 KB
- ad9695_fmc_01.svg
- 07 Apr 2022 16:07
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- ad9695_fmc_8.svg
- 24 Feb 2021 09:14
- 83.5 KB
- ad9695_fmc_clocking_0.svg
- 19 Jan 2021 13:27
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- ad9695_fmc_clocking_working.svg
- 07 Apr 2022 15:51
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- ad9695_fmc_zcu102_syncrona_setup.jpg
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- 07 Apr 2022 15:46
- 1009.5 KB
- ad_dds_1.svg
- 04 Feb 2021 19:55
- 46.7 KB
- ad_ip_jesd204_transport_adc.png
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- 23 Feb 2018 15:26
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- ad_ip_jesd204_transport_dac.png
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- 23 Feb 2018 15:26
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- adc_crc_ad7606b_c-16.png
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- 12 Jan 2023 13:42
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- adc_crc_ad7606c-18.png
- 1180×180
- 12 Jan 2023 13:35
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- adc_datapath_01.svg
- 07 Mar 2017 10:13
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- adc_fifo_write.svg
- 19 Feb 2015 18:28
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- adc_jesd.svg
- 02 Mar 2017 11:30
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- adc_lvds_1.svg
- 09 Aug 2016 15:55
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- adc_read_mode_ad7606b_c-16.png
- 1180×180
- 12 Jan 2023 14:18
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- adc_reg_mode_ad7606x_fam.png
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- 12 Jan 2023 14:19
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- adc_regmap_01.svg
- 07 Mar 2017 11:40
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- adc_status_ad7606b_c-16.png
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- 12 Jan 2023 13:37
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- adc_status_ad7606b_c-16_crc.png
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- 12 Jan 2023 13:53
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- adc_status_ad7606c-18_crc.png
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- 12 Jan 2023 14:00
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- adc_status_ad7606c18.png
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- 12 Jan 2023 13:40
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- adrv9371_1.svg
- 21 Oct 2016 10:35
- 164.2 KB
- adrv9371_2.svg
- 16 Mar 2018 09:51
- 160.6 KB
- adrv9371_3.svg
- 16 Mar 2018 09:52
- 158.2 KB
- axi_ad7606x_ip_diagr.svg
- 16 Jan 2023 20:03
- 46.5 KB
- axi_ad7616_ip.svg
- 29 Nov 2022 14:07
- 20.6 KB
- axi_ad7616_par.svg
- 30 Jun 2016 10:37
- 20 KB
- axi_ad7616_par_v2.svg
- 02 Aug 2016 13:43
- 22.8 KB
- axi_ad7616_ser.svg
- 30 Jun 2016 10:37
- 22.5 KB
- axi_ad7616_ser_v2.svg
- 02 Aug 2016 13:43
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- axi_ad9144.svg
- 01 Mar 2017 13:21
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- axi_ad9265.png
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- 21 Jul 2016 09:54
- 225 KB
- axi_ad9265_3.svg
- 09 Aug 2016 15:54
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- axi_ad9265_4.svg
- 16 Aug 2016 10:33
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- axi_ad9361_1.svg
- 15 Nov 2016 11:34
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- axi_ad9361_2.svg
- 15 Nov 2016 11:37
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- axi_ad9361_3.svg
- 27 Jun 2017 10:00
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- axi_ad9371_2.svg
- 16 Mar 2018 09:40
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- axi_ad9467.svg
- 02 Mar 2017 10:42
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- axi_ad9467_1.svg
- 02 Mar 2017 10:43
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- axi_ad9643.svg
- 28 Feb 2017 16:11
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- axi_ad9783.jpg
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- 23 Sep 2022 16:07
- 270 KB
- axi_ad9783_parallel_interface.jpg
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- 10 Jan 2022 17:33
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- axi_ad9963.svg
- 15 May 2017 15:03
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- axi_adc_decimate.svg
- 24 Aug 2017 10:22
- 56.2 KB
- axi_adc_trigger.svg
- 29 May 2017 10:06
- 49.7 KB
- axi_adc_trigger_diagram.png
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- 01 Sep 2020 07:47
- 220.1 KB
- axi_clkgen.svg
- 07 Jul 2017 14:56
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- axi_clkgen_1.svg
- 07 Jul 2017 14:59
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- axi_clock_monitor.png
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- 15 Feb 2022 12:28
- 16 KB
- axi_dac_interpolate.svg
- 24 Aug 2017 10:24
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- axi_dmac_block_diagram.png
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- 25 Feb 2018 11:06
- 49.7 KB
- axi_dmac_block_diagram.svg
- 30 Aug 2017 12:52
- 44.3 KB
- axi_fan_control_1.svg
- 22 Mar 2019 17:23
- 13.8 KB
- axi_fan_control_pvm_vs_temp.svg
- 27 Mar 2019 10:21
- 27.9 KB
- axi_logic_analyzer.svg
- 29 May 2017 09:09
- 43.7 KB
- axi_logic_analyzer_diagram.png
- 1392×792
- 04 Sep 2020 12:23
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- axi_logic_analyzer_trigger.png
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- 04 Sep 2020 12:34
- 135.9 KB
- axi_ltc235x_cmos_bd.png
- 1868×1399
- 15 Feb 2023 07:08
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- axi_ltc235x_cmos_bd.svg
- 20 Mar 2023 06:50
- 9 KB
- axi_ltc235x_cmos_detailed_archi.png
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- 15 Feb 2023 07:10
- 50.3 KB
- axi_ltc235x_cmos_detailed_archi.svg
- 20 Mar 2023 07:10
- 7.5 KB
- axi_pwm_gen.png
- 756×397
- 30 Jun 2021 10:55
- 39.6 KB
- axi_pwm_gen.svg
- 07 May 2021 17:38
- 59.2 KB
- base_platform.svg
- 02 Sep 2016 17:23
- 131.3 KB
- base_platform_11.svg
- 09 Sep 2016 14:18
- 136.3 KB
- base_platform_12.svg
- 09 Sep 2016 14:20
- 136.3 KB
- cn0561_hdl_0.svg
- 11 Feb 2022 16:44
- 93.8 KB
- cn0561_hdl_1.svg
- 13 Apr 2022 10:12
- 94.8 KB
- d2_phy_rec_tog.svg
- 17 Feb 2022 09:59
- 53.4 KB
- dac_datapath.svg
- 03 Nov 2017 11:05
- 19.5 KB
- dac_fifo_read.svg
- 19 Feb 2015 18:28
- 76.4 KB
- dac_jesd.svg
- 01 Mar 2017 12:12
- 15.1 KB
- dac_regmap.svg
- 10 Nov 2017 08:18
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- data_offload_bd.png
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- 11 Aug 2022 11:48
- 44.4 KB
- data_offload_ddr_bd.png
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- 11 Aug 2022 11:58
- 49.8 KB
- dds_basic.svg
- 04 Feb 2021 19:54
- 51 KB
- dds_clk_ratio_4.svg
- 04 Feb 2021 19:55
- 66.3 KB
- dds_dual_tone.svg
- 04 Feb 2021 19:55
- 56.7 KB
- dds_in_dac_core.svg
- 04 Feb 2021 19:57
- 114.5 KB
- fmcomms11_bd.svg
- 30 May 2019 15:09
- 194.9 KB
- fw_sync_basics.svg
- 04 Feb 2021 19:55
- 68.9 KB
- fw_sync_timing.png
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- 05 Feb 2021 15:51
- 49.5 KB
- hdl_adc_interface.jpg
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- 24 Nov 2014 20:11
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- hdl_cygwin_1.png
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- 24 Feb 2017 17:31
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- hdl_cygwin_2.png
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- 24 Feb 2017 17:31
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- hdl_cygwin_3.png
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- 24 Feb 2017 17:31
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- hdl_cygwin_4.png
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- 24 Feb 2017 17:31
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- hdl_cygwin_5.png
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- 24 Feb 2017 17:31
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- hdl_dac_interface.jpg
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- 05 Sep 2014 22:37
- 261 KB
- mii_recv.svg
- 21 Feb 2022 09:43
- 43.9 KB
- mii_rx.png
- 1200×120
- 16 Feb 2022 17:15
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- mii_transm.svg
- 21 Feb 2022 09:48
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- pcore_architecture.jpg
- 3832×1401
- 20 Oct 2014 20:04
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- pcore_bd.jpg
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- 12 Sep 2014 18:32
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- pcore_jesd.jpg
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- 24 Nov 2014 21:31
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- phy_rec_no_toggle.png
- 980×150
- 16 Feb 2022 16:19
- 15.9 KB
- phy_rec_simple.svg
- 20 Feb 2022 20:27
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- phy_rec_with_toggle.png
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- 16 Feb 2022 16:24
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- pulse_gen_external_sync.png
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- 07 May 2021 17:42
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- pulse_gen_load_config.png
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- 07 May 2021 17:20
- 45.1 KB
- pwm_gen_external_sync.png
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- 07 May 2021 17:44
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- pwm_gen_load_config.png
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- 07 May 2021 17:44
- 45.1 KB
- rfifo_hdl_1.svg
- 07 Nov 2017 09:15
- 83.4 KB
- rmii_transm.svg
- 21 Feb 2022 09:54
- 39 KB
- small_slave_big_master.svg
- 09 Mar 2021 14:38
- 13.8 KB
- source_sync_if_1.svg
- 23 Oct 2017 15:46
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- sysid1.svg
- 02 Oct 2019 12:12
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- time_diag_phy_receive.png
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- 16 Feb 2022 15:02
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- ultras_initial.jpg
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- 21 Feb 2019 08:36
- 159.3 KB
- ultras_structural.jpg
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- 21 Feb 2019 08:41
- 55 KB
- up_if_2.svg
- 20 Jun 2017 14:23
- 228.6 KB
- util_mii_to_rmii.drawio_3_.svg
- 16 Feb 2022 14:13
- 30.3 KB
- xcvr_conflict.jpg
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- 08 Dec 2021 10:50
- 52 KB
- xcvr_mapping_example.jpg
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- 08 Dec 2021 10:49
- 46.7 KB
- xcvr_rx_rearrangement.jpg
- 824×227
- 09 Nov 2022 07:09
- 55.5 KB
- xcvr_tx_rearrangement.jpg
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- 08 Dec 2021 10:52
- 53.2 KB
![[root]](/resources/fpga/xilinx/interposer/cn0188?ns=&tab_files=files&do=media&tab_details=view&image=resources%3Afpga%3Adocs%3Axcvr_rx_rearrangement.jpg){kind=link}
File
- Date:
- 09 Nov 2022 07:09
- Filename:
- xcvr_rx_rearrangement.jpg
- Photographer:
- Nagy, Laszlo
- Format:
- JPEG
- Size:
- 55KB
- Width:
- 824
- Height:
- 227
- References for:
- UTIL_ADXCVR core for Xilinx devices
resources/fpga/xilinx/interposer/cn0188.txt · Last modified: 09 Jan 2021 00:49 by Robin Getz