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resources:fpga:xilinx:interposer:ad9834 [28 Sep 2012 13:19]
AdrianC Added common section for describing the evaluation setup and System Demonstration Platform
resources:fpga:xilinx:interposer:ad9834 [21 Oct 2013 15:42]
LucianS changed source code (without Micrium uC-Probe), added Software Setup, remove programming with Impact
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 ====== Overview ====== ====== Overview ======
  
-This document presents the steps to setup an environment for using the **[[adi>​AD9834|EVAL-AD9834SDZ]]** evaluation board together with the Xilinx KC705 FPGA boardthe Xilinx Embedded Development Kit (EDK) and the [[http://​micrium.com/​page/​products/​tools/​probe|Micrium µC-Probe]] run-time monitoring tool. Below is presented a picture of the EVAL-AD9834SDZ Evaluation Board with the Xilinx KC705 board.+This document presents the steps to setup an environment for using the **[[adi>​AD9834|EVAL-AD9834SDZ]]** evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD9834SDZ Evaluation Board with the Xilinx KC705 board.
  
 {{ :​resources:​fpga:​xilinx:​interposer:​img_ad9834.jpg }} {{ :​resources:​fpga:​xilinx:​interposer:​img_ad9834.jpg }}
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   * [[adi>/​static/​imported-files/​user_guides/​UG-266.pdf|EVAL-AD9834SDZ evaluation board user guide]]   * [[adi>/​static/​imported-files/​user_guides/​UG-266.pdf|EVAL-AD9834SDZ evaluation board user guide]]
   * [[http://​www.xilinx.com/​products/​boards-and-kits/​EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]   * [[http://​www.xilinx.com/​products/​boards-and-kits/​EK-K7-KC705-G.htm | Xilinx KC705 FPGA board]]
-  * [[http://​micrium.com/​page/​products/​tools/​probe|Micrium uC-Probe]] 
  
 ====== Getting Started ====== ====== Getting Started ======
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 ===== Required Software ===== ===== Required Software =====
  
-  * Xilinx ISE 13.4 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack)+  * Xilinx ISE 14.6
-  * [[http://micrium.com/​page/​products/​tools/​probe|uC-Probe]] run-time monitoring tool+  * UART Terminal (Termite/Tera Term/Hyperterminal),​ baud rate 115200. 
 +  * The EVAL-AD9834 reference project for Xilinx KC705 FPGA. 
  
 ===== Downloads ===== ===== Downloads =====
- +<WRAP round download 80%> 
-  * {{:resources:​fpga:xilinx:​interposer:​ad9834_evalboard.zip|Reference Design Files}} +\\ 
- +  * **AD9834 Driver:** https://github.com/​analogdevicesinc/​no-OS/​tree/​master/​device_drivers/​AD9833 
-The following table presents a short description the reference design archive contents. +  * **AD9834 Commands:** https://​github.com/​analogdevicesinc/​no-OS/​tree/​master/​device_commands/​AD9833 
- +  ​* **Xilinx Boards Common Drivers:** https://​github.com/​analogdevicesinc/​no-OS/​tree/​master/​platform_drivers/​Xilinx/​SDP_Common 
-**Folder** **Description** +  * **EDK KC705 Reference ​project:** https://​github.com/​analogdevicesinc/​fpgahdl_xilinx/​tree/​master/​cf_sdp_kc705 
-| Bit | Contains the KC705 configuration file that can be used to program the system for quick evaluation| +\\ 
-| Microblaze | Contains the EDK 13.4 project for the Microblaze softcore that will be implemented in the KC705 FPGA. | +</​WRAP>​
-| Software | Contains the source files of the software ​project ​that will be run by the Microblaze processor.| +
-| uCProbeInterface | Contains the uCProbe interface and the .elf symbols file used by uC-Probe to access data from the Microblaze memory. | +
 ====== Run the Demonstration Project ====== ====== Run the Demonstration Project ======
  
-{{page>​ucprobe_common}} +===== Hardware setup =====
- +
-===== Demonstration Project User Interface ​===== +
- +
-The following figure presents the **uC-Probe** interface that can be used for monitoring and controlling the operation of the **EVAL-AD9834SDZ** evaluation board. +
- +
-{{ :​resources:​fpga:​altera:​bemicro:​ad9834_interface.png?​700 }} +
- +
-**Section A** is used to activate the board and monitor activity. The communication with the board is activated / deactivated by toggling the **//​ON/​OFF//​** switch. The **//​Activity//​** LED turns green when the communication is active. If the **//​ON/​OFF//​** switch is set to **//ON//** and the **//​Activity//​** LED is **//​BLACK//​** it means that there is a communication problem with the board. See the **Troubleshooting** section for indications on how to fix the communication problems. +
- +
-**Section B** is used to set or clear the bits and pins which affect the signal from the IOUT output. +
- +
-Programming Method: +
- +
-  * HW – selects the control pins to implement the register selection, reset, and DAC power-down functions. +
-  * SW – selects the control bits to implement the register selection, reset, and DAC power-down functions. +
- +
-Frequency control: +
- +
-  * F1 – FREQ1 register is used in the phase accumulator. +
-  * F0 – FREQ0 register is used in the phase accumulator. +
- +
-Phase control: +
- +
-  * P1 – PHASE1 register data is added to the output of the phase accumulator. +
-  * P0 – PHASE0 register data is added to the output of the phase accumulator. +
- +
-IOUT Output: +
- +
-  * Ramp – Triangle signal at the output. +
-  * Sin – Sinusoidal signal at the output. +
- +
-HW Pins: +
- +
-  * F1 / F0 – This pin controls which frequency register, FREQ0 or FREQ1, is used in the phase accumulator. +
-  * P1 / P0 – This pin controls which phase register, PHASE0 or PHASE1, is added to the phase accumulator output. +
- +
-Sleep: When this pin is high, the DAC is powered down. +
- +
-Reset: This pin resets the appropriate internal registers to 0. +
- +
-**Section C** is used to load values in the frequency and phase registers. +
-A frequency value is set using the corresponding dial and slider controls. ​ The dial sets the number of the digit to be modified and the slider sets the value of the selected digit. For example in order to set the value of 1234 Hz the following steps have to be performed (not necessarily in the listed order): +
- +
-  * put the dial to position 0 and move the slider to 4; +
-  * put the dial to position 1 and move the slider to 3; +
-  * put the dial to position 2 and move the slider to 2; +
-  * put the dial to position 3 and move the slider to 1. +
- +
-**Section D** is used to set or clear the bits which affect the signal from the SIGN BIT OUT output. +
- +
-Sign Bit Output Options: +
- +
-  * Enable / Disable – enables / disables the SIGN BIT OUT pin. +
-  * Comparator / DAC – connects the on-board comparator / the MSB of the DAC to the SIGN BIT OUT pin. +
-  * MSB / MSB/2 – Outputs MSB / MSB/2 of the DAC to the SIGN BIT OUT pin. +
- +
-**Section E** is used to select the sleep mode of the circuit. +
- +
-**Section F** is used to activate and control the Frequency Sweep function. +
- +
-Sweep ON / Sweep OFF: Turn ON / OFF the sweep function. +
- +
-Start / Stop: Start / Stop the sweep function.+
  
-Start Frequency: Value of the start frequency.+<WRAP round important 80%> 
 +\\ 
 +Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage ​of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page. 
 +</​WRAP>​
  
-Stop Frequency: Value of the stop frequency.+  * Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector. 
 +  * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-Step Frequency: Value of the increment size.+===== Reference Project Overview ===== 
 +The following commands were implemented in this version of EVAL-AD9834 reference project for Xilinx KC705 FPGA board. 
 +^ Command ^ Description ^ 
 +| **help?** | Displays all available commands. | 
 +| **output=** | Selects the type of output. Accepted values:\\ 0 - Sinusoid.(default)\\ 1 - Triangle. | 
 +| **output?** | Displays the type of output. | 
 +| **loadFreqReg=** | Loads a frequency value in one selected register. Accepted values:\\ Register number:\\ 0 - Frequency ​Register 0.\\ 1 - Frequency Register 1.\\ Value:\\ 0 .. 37 500 000 - the frequency value in Hz. | 
 +| **freqRegVal?​** | Displays the value from one selected frequency register. ​ Accepted values:\\ Register number:\\ 0 - Frequency Register 0.\\ 1 - Frequency Register 1. | 
 +| **loadPhaseReg=** | Loads a phase value in one selected register. Accepted values:\\ Register number:\\ 0 - Phase Register 0.\\ 1 - Phase Register 1.\\ Value:\\ 0 .. 2PI - the phase value in radians. | 
 +| **phaseRegVal?​** | Displays the value from one selected phase register. ​ Accepted values:\\ Register number:\\ 0 - Phase Register 0.\\ 1 - Phase Register 1. | 
 +| **freqRegNo=** | Select the frequency register to be used. Accepted values:\\ Register number:\\ 0 - Frequency Register 0.\\ 1 - Frequency Register 1. | 
 +| **freqRegNo?​** | Displays the selected frequency register. | 
 +| **phaseRegNo=** | Select the phase register to be used. Accepted values:\\ Register number:\\ 0 - Phase Register 0.\\ 1 - Phase Register 1. | 
 +| **phaseRegNo?​** | Displays the selected phase register. | 
 +| **sleepMode=** | Select one sleep mode. Accepted values:\\ Sleep mode:\\ Soft method:\\ 0 - No power-down.(default)\\ 1 - DAC powered down. \\ 2 - Internal clock disabled. \\ 3 - DAC powered down and Internal clock disabled. \\ Hard method: \\ 0 - No power-down.(default)\\ 1 - DAC powered down. | 
 +| **sleepMode?​** | Displays the selected sleep mode. | 
 +| **program=** | Sets the programming method. Accepted values:\\ Method:\\ 0 - Soft programming method.(default)\\ 1 - Hard programming method. | 
 +| **program?​** | Displays the programming method. | 
 +| **logicOut=** | Sets the logic output type. Accepted values:\\ Logic output type:\\ 0 - High impedance.(default)\\ 1 - DAC data MSB/2.\\ 2 - DAC data MSB.\\ 3 - Comparator. | 
 +| **logicOut?​** | Displays ​the logic output type
 + 
  
-Delay: Value of the delay between each frequency increment.+Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
  
-===== Troubleshooting =====+The following image shows a generic list of commands in a serial terminal connected to Xilinx KC705 FPGA's UART peripheral. 
 +{{ :​resources:​fpga:​xilinx:​interposer:​Terminal_KC705.jpg?​ }}
  
-In case there is a communication problem with the board the follwing actions can be perfomed in order to try to fix the issues: +===== Software Project Setup ===== 
-  * Check that the evaluation board is powered as instructed in the board'​s user guide. +{{page>​import_workspace}}
-  * In uC-Probe refresh the symbols file by right-clicking on the **//System Browser//** window and selecting **//Refresh Symbols//​**. +
-  * If the communication problem persists even after performing the previous steps, restart the uC-Probe application and try to run the interface again.+
  
 ====== More information ====== ====== More information ======
   * [[resources:​tools-software:​linux-drivers:​iio-dds:​ad9834|AD9834 IIO Direct Digital Synthesis Linux Driver]]   * [[resources:​tools-software:​linux-drivers:​iio-dds:​ad9834|AD9834 IIO Direct Digital Synthesis Linux Driver]]
 {{page>​ez_common}} {{page>​ez_common}}
resources/fpga/xilinx/interposer/ad9834.txt · Last modified: 21 Oct 2013 15:42 by LucianS