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--- resources:fpga:xilinx:interposer:ad9789 [19 Jun 2012 20:59] – created rejeesh kutty
+++ resources:fpga:xilinx:interposer:ad9789 [28 Jan 2021 19:14] (current) – update arrow links after their web site update Robin Getz
@@ Line 3: / Line 3: @@
 ===== Introduction =====
-The [[adi>AD9739A]] is a 14-bit, 2.5GSPS high performance RF digital-to-analog converter (DAC) capable of synthesizing wideband signals from DC up to 3 GHz. This reference design includes a DDS generator that drives both ports of the device. The programming is done via the USB-SPI interface.
+The [[adi>AD9789]] is a flexible four channel QAM encoder, interpolator and upconverter combined with a high performance, 2.4GSPS, 14-bit, RF digital-to-analog converter (DAC). This reference design includes DDS generators that drives all channels of the device. The programming is done via the USB-SPI interface.
+===== Supported Devices =====
+  * [[adi>en/digital-to-analog-converters/high-speed-da-converters/ad9789/products/EVAL-AD9789/eb.html|AD9789 Evaluation Board]]
+  * [[adi>AD-DAC-FMC|DAC FMC Interposer Board]]
+===== Supported Carriers =====
+  * [[xilinx>ML605]]
-**HW Platform(s):** [[http://www.xilinx.com/ml605|Virtex-6 ML605 (Xilinx)]] or [[http://www.xilinx.com/kc705|Kintex-7 KC705 (Xilinx)]] or [[http://www.xilinx.com/vc707|Virtex-7 Vc707 (Xilinx)]] and [[http://www.analog.com/en/digital-to-analog-converters/da-converters/ad9739a/products/EVAL-AD9739A/eb.html|AD9739A Evaluation Board (ADI)]], [[http://www.analog.com/en/digital-to-analog-converters/da-converters/ad-dac-fmc/products/product.html|DAC FMC Interposer Board (ADI)]] \\
-**System:** Microblaze, AXI, UART
 ===== Quick Start Guide =====
-The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal, ADI DAC software and the programmer (IMPACT). The notes below refer to ML605, but the procedure is same for all the boards.
+The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal, ADI DAC software and the programmer (IMPACT).
 ==== Required Hardware ====
-  * ML605/KC705/VC707 board
+  * ML605 board
-  * AD9739A-EBZ board & Power supply
+  * AD9789-EBZ board & Power supply
   * DAC FMC interposer board
-  * Signal/Clock generator (2.5GHz)
+  * Signal/Clock generator (2.4GHz)
   * Spectrum Analyzer
 ==== Required Software ====
-  * Xilinx ISE 13.2 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
+  * Xilinx ISE 14.1 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
-  * ADI DPG DAC Software Suite [[http://www.analog.com/en/digital-to-analog-converters/da-converters/products/evaluation-boardstools/CU_eb_DPG_high_speed_DAC_eval_platform/resources/fca.html|available here]].
+  * ADI DPG DAC Software Suite [[adi>en/digital-to-analog-converters/da-converters/products/evaluation-boardstools/CU_eb_DPG_high_speed_DAC_eval_platform/resources/fca.html|(available here)]].
 ==== Bit file ====
-  * Download the gzip file and extract the **sw/cf_ad9739a_ebz<board>.bit** file.
+  * Download the gzip file and extract the **sw/cf_ad9789_ebz.bit** file.
 ==== Running Demo (SDK) Program ====
-<note tip>If you are not familiar with ML605 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards/ml605/reference_designs.htm]] for details.
-</note>
 To begin make the following connections (see image below):
-  * Connect the AD9739A-EBZ board to the FMC Interposer board.
+  * Connect the AD9789-EBZ board to the FMC Interposer board.
   * Connect the interposer board to the **FMC-LPC** connector of ML605 board.
-  * Connect power to ML605 and the AD9739A-EBZ boards.
+  * Connect power to ML605 and the AD9789-EBZ boards.
   * Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on ML605.
-  * Connect a USB cable to the AD9739A-EBZ board.
+  * Connect a USB cable to the AD9789-EBZ board.
-  * Connect an external clock source to AD9739A-EBZ board's J3 SMA connector.
+  * Connect an external clock source to AD9789-EBZ board's S1 (HF_DACCLK) SMA connector.
-  * Connect a spectrum analyzer to AD9739A-EBZ board's J1 SMA connector.
+  * Connect a spectrum analyzer to AD9789-EBZ board's S5 (AOUT_DAC-) SMA connector.
-Setup the clock source to be 2.5GHz. If you wish to run the device at a different clock rate, please change the SDK c program accordingly. After the hardware setup, turn the power on to the ML605 and the AD9739A-EBZ boards.
+Setup the clock source to be 2.4GHz/6dBm. After the hardware setup, turn the power on to the ML605 and the AD9789-EBZ boards.
-{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_setup.jpg?200|Hardware setup}}
+{{:resources:fpga:xilinx:interposer:cf_ad9789_ebz_setup.jpg?200|Hardware setup}}
-Start ADI- AD9739A SPI program (see screenshot below)-
+The reference design primarily supports four modes of operation.
-  * (1) click on "Run Continously" button.
+| Mode | Key-Select   | Bus-Width | Data-Width | Data-Format | First Block Enabled  | Description  |
-  * (2) click on "MU_ENA" button.
+| 0x0  | 'a'          | 32        | 8          | Real        | QAM mapper           | Channelizer Mode. |
-  * (3) make sure that "MU_LCK" has turned green.
+| 0x1  | 'b'          | 32        | 8          | Complex     | SRRC filter          | Channelizer Mode. |
+| 0x2  | 'c'          | 32        | 16         | Complex     | Interpolation Filter | Channelizer Mode. |
+| 0x3  | 'd'          | 32        | 16         | Complex     | N/A                  | QDUC Mode. |
-{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_usb_spi.jpg?200|Hardware setup}}
+The reference design is NOT fully verified across all the modes. The delay/latency parameters may have to be adjusted depending on various features selected.
-Start IMPACT, and initialze the JTAG chain. The program should recognize the Virtex 6 device (see screenshot below). Start a UART terminal (set to 57600 baud rate) and then program the device.
+==== QAM Mapper Mode ====
-{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_impact.jpg?200|IMPACT}}
+==== SRRC Filter Mode ====
+==== Interpolation Filter Mode ====
+Start ADI- AD9789 SPI program (see screenshot below)-
+  * Click on "Run Continously" button.
+  * Interface Control: Set DCO_INV to OFF position (change it to ON if the spectrum has unwanted spurs).
+  * Interface Control: Set I/F_MODE to Channelizer mode.
+  * Interface Control: Set CHANPRI to ON position (enabled).
+  * Data Control: Set Coding to Binary position.
+  * Data Control: Set Data Width to 16-Bit mode.
+  * Data Control: Set I/O-Data Path to Complex.
+  * Data Control: Make sure BusWidth is set to 32.
+  * Data Control: Set Latency to 1.
+  * Channel Select: Enable all channnels.
+  * Bypass: Enable QAM Mapper, SRRC filter and filter 4 bypass.
+  * Summing Junction Scalar Input Scalar: Set 2.6 Multiplier Scale to 16. Note that this value must be set so that the saturation counter is always read as 0x0. You may clear the saturation register by clicking on the knob right next to it.
+  * NCO Frequency Tuming Words: Make sure the central frequency is 834MHz on all channels.
+  * Interpolating BPF Center Frequency: Set it to 834MHz click twice on the button to the right for the changes to take effect.
+  * Reference/Sample/Sync Clock Control: Make sure DCODIV is set to 0x1.
+  * Reference/Sample/Sync Clock Control: Set DSCPHZ to 0x0, click twice on PARAMNEW to take effect.
+  * Reference/Sample/Sync Clock Control: Set SNCPHZ to 0x3, click twice on PARAMNEW to take effect.
+{{:resources:fpga:xilinx:interposer:cf_ad9789_ebz_intp_spi.jpg?200|SPI setup}}
+  * Start a UART terminal (57600 baud rate).
+  * Start IMPACT/XMD then program the device.
 If programming was successful, you should be seeing messages appear on the terminal as shown in figure below.
-{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_uart.jpg?200|Terminal}}
+{{:resources:fpga:xilinx:interposer:cf_ad9789_ebz_intp_uart.jpg?200|Terminal}}
-Now enable the receivers via the ADI- AD9739A SPI program (see screenshot above)-
+Select 'c' for the interpolation filter mode. The spectrum should appear as shown below. The DDS is set to 500KHz to 2000KHz.
-  * (4) click on "RCV_ENA" button.
+{{:resources:fpga:xilinx:interposer:cf_ad9789_ebz_intp_spectrum.jpg?200|Terminal}}
-  * (5) click on "RCV_LOOP" button.
-  * (6) make sure that "RCV_LCK" and "RCV_TRACK" has turned green.
-After DDS is enabled, you should see the spectrum analyzer displaying the 300MHz tone.
+==== QDUC Mode ====
-{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_spectrum.gif?200|Terminal}}
+Start ADI- AD9789 SPI program (see screenshot below)-
+  * Click on "Run Continously" button.
+  * Interface Control: Set DCO_INV to OFF position (change it to ON if the spectrum has unwanted spurs).
+  * Interface Control: Set I/F_MODE to QDUC mode.
+  * Interface Control: Set CHANPRI to ON position (enabled).
+  * Data Control: Set Coding to Binary position.
+  * Data Control: Set Data Width to 16-Bit mode.
+  * Data Control: Set I/O-Data Path to Complex.
+  * Data Control: Make sure BusWidth is set to 32.
+  * Data Control: Set Latency to 1.
+  * Channel Select: Enable channel 0, disable all the other channnels.
+  * Bypass: Enable QAM Mapper, SRRC filter and all other filters bypass.
+  * Summing Junction Scalar Input Scalar: Set 2.6 Multiplier Scale to 45. Note that this value must be set so that the saturation counter is always read as 0x0. You may clear the saturation register by clicking on the knob right next to it.
+  * NCO Frequency Tuming Words: Make sure the central frequency is 834MHz on channel 0.
+  * Interpolating BPF Center Frequency: Set it to 834MHz click twice on the button to the right for the changes to take effect.
+  * Reference/Sample/Sync Clock Control: Make sure DCODIV is set to 0x1.
+  * Reference/Sample/Sync Clock Control: Set DSCPHZ to 0x0, click twice on PARAMNEW to take effect.
+  * Reference/Sample/Sync Clock Control: Set SNCPHZ to 0x3, click twice on PARAMNEW to take effect.
+{{:resources:fpga:xilinx:interposer:cf_ad9789_ebz_qduc_spi.jpg?200|SPI setup}}
+  * Start a UART terminal (57600 baud rate).
+  * Start IMPACT/XMD then program the device.
+If programming was successful, you should be seeing messages appear on the terminal as shown in figure below.
+{{:resources:fpga:xilinx:interposer:cf_ad9789_ebz_qduc_uart.jpg?200|Terminal}}
+Select 'd' for the qduc mode. The spectrum should appear as shown below. The DDS is set to 3MHz.
+{{:resources:fpga:xilinx:interposer:cf_ad9789_ebz_qduc_spectrum.jpg?200|Terminal}}
 ===== Using the reference design =====
@@ Line 79: / Line 144: @@
 ==== Functional description ====
-The reference design consists of a DDS module and a lvds interface.
+The reference design consists of a DDS module and a lvds interface. The DDS module consists of a Xilinx DDS core and DDR based DDS. It is possible to change the output data delay with respect to the DCO clock, as well as the FS to data delay. See the regmap file and the SDK c file.
-The DDS module consists of a Xilinx DDS core and DDR based DDS. Internally the DDS runs at fDAC/3 clock. The output samples are interleaved and driven by the lvds interface.
 ==== Registers ====
@@ Line 89: / Line 152: @@
 ===== Downloads =====
-{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz.tar.gz|ML605 Reference Design Source Code}}\\
+FPGA Referece Designs:
-{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_kc705.tar.gz|KC705 Reference Design Source Code}}\\
+<WRAP round download 80%>
-{{:resources:fpga:xilinx:interposer:cf_ad9739a_ebz_vc707.tar.gz|VC707 Reference Design Source Code}}\\
+  * **ML605 (source files) ** {{:resources:fpga:xilinx:interposer:cf_ad9789_ebz_edk_14_4_2013_03_25.tar.gz}}
+  * **ML605 (bit/sw files) ** {{:resources:fpga:xilinx:interposer:cf_ad9789_ebz_sw_14_4_2013_03_25.tar.gz}}
+</WRAP>
+Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
-===== Notes =====
+<WRAP round help 80%>
+  * Questions? [[ez>fpga|Ask Help & Support]].
+</WRAP>
-The following two files are removed from the tar file.
-  * pcores/cf_ad9739a_core_v1_00_a/netlist/cf_ddsx.ngc
-  * pcores/cf_ad9739a_core_v1_00_a/hdl/verilog/cf_ddsx.v
-To use the reference design as it is, re-generate the Xilinx DDS core for a single sine output (16bit) in full range mode.
 ===== Tar file contents =====
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
+The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
 | license.txt | ADI license & copyright information. |
@@ Line 118: / Line 182: @@
 ===== More information =====
-  * [[http://www.vita.com/fmc.html|VITA's FMC info]]
+  * [[http://www.vita.com/fmc|VITA's FMC info]]
   * [[ez>community/fpga|Ask questions about the FPGA reference design]]

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