This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revisionNext revisionBoth sides next revision | ||
resources:fpga:xilinx:interposer:ad9789 [19 Jun 2012 21:53] – updated rejeesh kutty | resources:fpga:xilinx:interposer:ad9789 [12 Jun 2017 15:01] – Lars-Peter Clausen | ||
---|---|---|---|
Line 5: | Line 5: | ||
The [[adi> | The [[adi> | ||
- | **HW Platform(s): | + | ===== Supported Devices ===== |
- | **System:** Microblaze, AXI, UART | + | |
+ | | ||
+ | * [[http:// | ||
+ | |||
+ | ===== Supported Carriers ===== | ||
+ | |||
+ | | ||
+ | |||
===== Quick Start Guide ===== | ===== Quick Start Guide ===== | ||
Line 58: | Line 66: | ||
==== QAM Mapper Mode ==== | ==== QAM Mapper Mode ==== | ||
- | The interface is minimally tested. The functionality is not tested! | ||
==== SRRC Filter Mode ==== | ==== SRRC Filter Mode ==== | ||
- | The interface is minimally tested. The functionality is not tested! | ||
==== Interpolation Filter Mode ==== | ==== Interpolation Filter Mode ==== | ||
Line 69: | Line 75: | ||
* Click on "Run Continously" | * Click on "Run Continously" | ||
- | * Interface Control: Set DCO_INV to On position. | + | * Interface Control: Set DCO_INV to OFF position |
* Interface Control: Set I/F_MODE to Channelizer mode. | * Interface Control: Set I/F_MODE to Channelizer mode. | ||
* Interface Control: Set CHANPRI to ON position (enabled). | * Interface Control: Set CHANPRI to ON position (enabled). | ||
Line 104: | Line 110: | ||
* Click on "Run Continously" | * Click on "Run Continously" | ||
- | * Interface Control: Set DCO_INV to On position. | + | * Interface Control: Set DCO_INV to OFF position |
* Interface Control: Set I/F_MODE to QDUC mode. | * Interface Control: Set I/F_MODE to QDUC mode. | ||
* Interface Control: Set CHANPRI to ON position (enabled). | * Interface Control: Set CHANPRI to ON position (enabled). | ||
Line 146: | Line 152: | ||
===== Downloads ===== | ===== Downloads ===== | ||
- | {{: | + | FPGA Referece Designs: |
+ | <WRAP round download 80%> | ||
+ | * **ML605 (source files) ** {{: | ||
+ | * **ML605 (bit/sw files) ** {{: | ||
+ | </ | ||
+ | Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[http:// | ||
- | ===== Notes ===== | + | <WRAP round help 80%> |
+ | * Questions? [[http:// | ||
+ | </ | ||
- | The following two files are removed from the tar file. | ||
- | * pcores/ | ||
- | * pcores/ | ||
- | To use the reference design as it is, re-generate the Xilinx DDS core for a single sine output (16bit) in full range mode. | ||
===== Tar file contents ===== | ===== Tar file contents ===== | ||
Line 173: | Line 182: | ||
===== More information ===== | ===== More information ===== | ||
- | * [[http:// | + | * [[http:// |
* [[ez> | * [[ez> | ||