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The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. It is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired. The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. This reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM on KC705. It allows programming the device and monitoring it's internal registers via SPI.
HW Platform(s): Kintex-7 KC705 (Xilinx), AD9250 Evaluation Board (ADI), ADC FMC Interposer Board (ADI)
System: Microblaze, AXI, UART
The reference design zip file contains a bit file combined with a SDK elf file for a quick demonstration of the programming and data capture. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT).
The reference design contains UCF files for the Rev. B board, CVT-ADC-FMC-INTPZB.
Please do the following modifications on the AD9250 evaluation board.
To begin make the following connections (see image below):
The quick start bit file configures the AD9250 for all test modes and verifies the captured data accordingly. After the hardware setup, turn the power on to the KC705 and the AD9250-EBZ boards.
Start IMPACT, and initialze the JTAG chain. The program should recognize the Kintex 7 device. Start a UART terminal (set to 57600 baud rate) and then program the device. If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD9250, the program checks data capture on various test modes.
After patterns and prbs sequences are verified, if no errors are present, you may use the chipscope busplot to see the captured signal (see below). The ADC data is available on pins [15:0] and [31:16] of UNIT:1 of chipscope.
The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below.
The reference design consists of two pcores. The JESD core consists of the GTX units and the Xilinx JESD 204 IP core. The AD9250 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface.
The ADC interface captures and buffers data from the JESD core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
The JESD core and AD9250 core has an AXI lite interface that allows control and monitoring of the capture process.
Please refer to the regmap.txt file in the pcores directory.
The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design.
KC705 Reference Design Source Code
Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. For help and support, please use Engineer Zone.
The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.
license.txt | ADI license & copyright information. |
system.mhs | MHS file. |
system.xmp | XMP file (use this file to build the reference design). |
data/ | UCF file and/or DDR MIG project files. |
docs/ | Documentation files (Please note that this wiki page is the documentation for the reference design). |
sw/ | Software (Xilinx SDK) & bit file(s). |
cf_lib/edk/pcores/ | Reference design core file(s) (Xilinx EDK). |