AD9250 Evaluation Board, ADC-FMC Interposer & Xilinx KC705 Reference Design

Introduction

The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. It is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired. The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. This reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM on KC705. It allows programming the device and monitoring it's internal registers via SPI.

HW Platform(s): Kintex-7 KC705 (Xilinx), AD9250 Evaluation Board (ADI), ADC FMC Interposer Board (ADI)
System: Microblaze, AXI, UART

Quick Start Guide

The reference design zip file contains a bit file combined with a SDK elf file for a quick demonstration of the programming and data capture. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT).

Required Hardware

KC705 board
AD9250-EBZ board & Power supply
ADC FMC interposer board
Signal/Clock generator (reference clock input, 250MHz)
Signal generator (analog input, for data capture)

Required Software

Xilinx ISE (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.

Bit file

Download the gzip file and extract the sw/cf_ad9250_ebz.bit file.

Board Modifications

If you have a Rev. A version of the FMC interposer board, please do the following modifications on the board.

Populate R209 (0ohm) and make sure R211 is NOT populated.
Insert (cut the traces) 33ohm resistors on U201 (UG3308) Y ports (pins 11 through 17).
Make sure that R201 through R207 are NOT populated.
Please change the UCF file as follows:

NET rxdata_p[1] LOC = “E4”;
NET rxdata_n[1] LOC = “E3”;
NET rxdata_p[0] LOC = “B6”;
NET rxdata_n[0] LOC = “B5”;
NET rxsync_p LOC = “C24” | IOSTANDARD = “LVDS_25”;
NET rxsync_n LOC = “B24” | IOSTANDARD = “LVDS_25”;
NET rxsysref_p LOC = “G18” | IOSTANDARD = “LVDS_25”;
NET rxsysref_n LOC = “F18” | IOSTANDARD = “LVDS_25”;

NET spi_ctrl LOC = “H15” | IOSTANDARD = “LVCMOS25”;
NET spi_csn[0] LOC = “F13” | IOSTANDARD = “LVCMOS25”;
NET spi_csn[1] LOC = “K14” | IOSTANDARD = “LVCMOS25”;
NET spi_clk LOC = “L12” | IOSTANDARD = “LVCMOS25”;
NET spi_mosi LOC = “L13” | IOSTANDARD = “LVCMOS25”;
NET spi_miso LOC = “G13” | IOSTANDARD = “LVCMOS25”;

If you have a Rev. B version of the interposer board use as it is. Though Rev. A has been tested, the reference design only contains UCF file for the Rev. B board.

NET rxdata_p[1] LOC = “B6”;
NET rxdata_n[1] LOC = “B5”;
NET rxdata_p[0] LOC = “D6”;
NET rxdata_n[0] LOC = “D5”;
NET rxsync_p LOC = “C29” | IOSTANDARD = “LVDS_25”;
NET rxsync_n LOC = “B29” | IOSTANDARD = “LVDS_25”;
NET rxsysref_p LOC = “D29” | IOSTANDARD = “LVDS_25”;
NET rxsysref_n LOC = “C30” | IOSTANDARD = “LVDS_25”;

NET spi_ctrl LOC = “K13” | IOSTANDARD = “LVCMOS25”;
NET spi_csn[0] LOC = “B18” | IOSTANDARD = “LVCMOS25”;
NET spi_csn[1] LOC = “A18” | IOSTANDARD = “LVCMOS25”;
NET spi_clk LOC = “G17” | IOSTANDARD = “LVCMOS25”;
NET spi_mosi LOC = “A17” | IOSTANDARD = “LVCMOS25”;
NET spi_miso LOC = “A16” | IOSTANDARD = “LVCMOS25”;

Please do the following modifications on the AD9250 evaluation board.

Remove R609.
Remove R610.
Remove R604.
Remove R601.

Running Demo (SDK) Program

To begin make the following connections (see image below):

Connect the AD9250-EBZ board to the FMC Interposer board.
Connect the interposer board to the FMC-HPC connector of KC705 board.
Connect power to KC705 and the AD9250-EBZ boards.
Connect two USB cables from the PC to the JTAG and UART USB connectors on KC705.
Connect an external clock source 250MHz (5dBm) to AD9250-EBZ board's J505 SMA connector.
Connect signal generators to the AIN-A/AIN-B, J301/J303 SMA connectors.

The quick start bit file configures the AD9250 for all test modes and verifies the captured data accordingly. After the hardware setup, turn the power on to the KC705 and the AD9250-EBZ boards.

Start IMPACT, and initialze the JTAG chain. The program should recognize the Kintex 7 device. Start a UART terminal (set to 57600 baud rate) and then program the device. If programming was successful, you should be seeing messages appear on the terminal as shown in figure below. After programming the AD9250, the program checks data capture on various test modes.

After patterns and prbs sequences are verified, if no errors are present, you may use the chipscope busplot to see the captured signal (see below). The ADC data is available on pins [15:0] and [31:16] of UNIT:1 of chipscope.

Using the reference design

The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below.

The reference design consists of two pcores. The JESD core consists of the GTX units and the Xilinx JESD 204 IP core. The AD9250 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface.

The ADC interface captures and buffers data from the JESD core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.

The JESD core and AD9250 core has an AXI lite interface that allows control and monitoring of the capture process.

Registers

Please refer to the regmap.txt file in the pcores directory.

Good To Know

The PN9/PN23 sequences are not compatible with O.150. Please use the equations given in the reference design.

Downloads

KC705 Reference Design Source Code

Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. For help and support, please use Engineer Zone.

Tar file contents

The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.

license.txt	ADI license & copyright information.
system.mhs	MHS file.
system.xmp	XMP file (use this file to build the reference design).
data/	UCF file and/or DDR MIG project files.
docs/	Documentation files (Please note that this wiki page is the documentation for the reference design).
sw/	Software (Xilinx SDK) & bit file(s).
cf_lib/edk/pcores/	Reference design core file(s) (Xilinx EDK).

Wiki

Analog Devices Wiki

Table of Contents

AD9250 Evaluation Board, ADC-FMC Interposer & Xilinx KC705 Reference Design

Introduction