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resources:fpga:xilinx:interposer:ad9116 [16 Nov 2012 16:54] – [Introduction] fix dead links Lars-Peter Clausenresources:fpga:xilinx:interposer:ad9116 [03 Jan 2013 20:42] – external edit
Line 47: Line 47:
 ==== Running Demo (SDK) Program ==== ==== Running Demo (SDK) Program ====
  
-<note tip>If you are not familiar with ML605 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards/ml605/reference_designs.htm]] for details. +<WRAP tip>If you are not familiar with ML605 and/or Xilix tools, please visit\\ [[http://www.xilinx.com/products/boards/ml605/reference_designs.htm]] for details. 
-</note>+</WRAP>
  
 Extract the project from the archive file (AD911x.zip) to the location you desire.  Extract the project from the archive file (AD911x.zip) to the location you desire. 
Line 133: Line 133:
   - **Section 13** User must press the button in order for the AD9512 related modifications to take place   - **Section 13** User must press the button in order for the AD9512 related modifications to take place
  
-<note important>+<WRAP important>
   * If you drag a slider and it doesn't change the value in the numeric indicator next to it, please press Stop and then Play again. At the bottom of the screen, the bytes/sec should be increasing with 200 per second. If they increase only with 50 per second, please press Stop and Play again.   * If you drag a slider and it doesn't change the value in the numeric indicator next to it, please press Stop and then Play again. At the bottom of the screen, the bytes/sec should be increasing with 200 per second. If they increase only with 50 per second, please press Stop and Play again.
   * If you receive (Pc Port Open) at the bottom of the screen, please press Stop, close your COM port, reprogram the FPGA, launch the software and try again.   * If you receive (Pc Port Open) at the bottom of the screen, please press Stop, close your COM port, reprogram the FPGA, launch the software and try again.
   * In **Section 10** please select DIVSEL so that (DCLKIO / 2^n) is between 0.5 MHz and 4 MHz for optimal Calibration results   * In **Section 10** please select DIVSEL so that (DCLKIO / 2^n) is between 0.5 MHz and 4 MHz for optimal Calibration results
-</note>+</WRAP>
  
 ===== Downloads ===== ===== Downloads =====
 {{:resources:fpga:xilinx:interposer:ad9116.zip|Reference design source code}} {{:resources:fpga:xilinx:interposer:ad9116.zip|Reference design source code}}
  
resources/fpga/xilinx/interposer/ad9116.txt · Last modified: 31 Jan 2024 09:53 by iulia Moldovan

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