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resources:fpga:xilinx:interposer:ad5541a [06 Sep 2013 15:50] – added link to EDK KC705 reference project on Github Lucian Sinresources:fpga:xilinx:interposer:ad5541a [01 Oct 2013 14:20] – [Hardware setup] Lucian Sin
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 <WRAP round download 80%> <WRAP round download 80%>
 \\ \\
-  * {{:resources:fpga:xilinx:interposer:cf_ad5541a_kc705.zip|Reference Design Files}} +  * **AD5541A Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD5446 
-  * **AD5541A Driver:** https://github.com/analogdevicesinc/no-OS/tree/master/device_drivers/AD5541A +  * **AD5541A Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5446
-  * **AD5541A Commands:** https://github.com/analogdevicesinc/no-OS/tree/master/device_commands/AD5541A+
   * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common   * **Xilinx Boards Common Drivers:** https://github.com/analogdevicesinc/no-OS/tree/master/platform_drivers/Xilinx/SDP_Common
   * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705   * **EDK KC705 Reference project:** https://github.com/analogdevicesinc/fpgahdl_xilinx/tree/master/cf_sdp_kc705
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   * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.   * Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
  
-===== Quick start evaluation ===== +<WRAP round important 80%>
-For a quick start evaluation, run the **download.bat** script located in the **SDK/SDK_Workspace/bin** folder provided within the Reference Design Files.  This script uses XMD to program the FPGA with the HDL Reference Design and download the Software Reference Design into the DDR. +
- +
-<WRAP round info 80%>+
 \\ \\
-The **download.bat** script assumes that the Xilinx ISE Design Suite 14.6 is installed at this path: **C:/Xilinx/14.6**. If the installation path on your computer is different, please modify the script accordingly.+The EVAL-AD5542A evaluation board will be powered from PCs USB interface (LK8 position=A, LK9 position=B, LK7 position=B, LK3 position=A, LK2 position=A).
 </WRAP> </WRAP>
- 
-If programming was successful, you should be seeing the command messages appear on the terminal. 
 ===== Reference Project Overview ===== ===== Reference Project Overview =====
 The following commands were implemented in this version of EVAL-AD5541A reference project for Xilinx KC705 FPGA board. The following commands were implemented in this version of EVAL-AD5541A reference project for Xilinx KC705 FPGA board.
 ^ Command ^ Description ^ ^ Command ^ Description ^
 | **help?** | Displays all available commands. | | **help?** | Displays all available commands. |
-| **voltage=** | Sets the DAC output voltage. Accepted values:\\ 0 .. 2500 - desired output voltage in milivolts. | +| **register=** | Writes to the DAC register. Accepted values:\\ 0 .. 65535 - the value written to the DAC. |
-| **voltage?** |  Displays last written voltage value to the DAC. | +
-| **register=** | Writes to the DAC register. Accepted values:\\ 0 .. 65535 -  the value written to the DAC. |+
 | **register?** | Displays last written value in the DAC register. | | **register?** | Displays last written value in the DAC register. |
 +| **voltage=** | Sets the DAC output voltage. Accepted values:\\ 0 .. +2500 - desired output voltage in milivolts. |
 +| **voltage?** | Displays last written voltage value to the DAC. |
 +| **ldacPin=** | Sets the output value of LDAC pin. Accepted values:\\ 0 - sets LDAC pin low.(default)\\ 1 - sets LDAC pin high. |
 +| **ldacPin?** | Displays the value of LDAC pin. |
 +| **clrPin=** | Sets the output value of CLR pin. Accepted values:\\ 0 - sets CLR pin low.\\ 1 - sets CLR pin high.(default) |
 +| **clrPin?** | Displays the value of CLR pin. |
 +
 +
  
 Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA. Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
resources/fpga/xilinx/interposer/ad5541a.txt · Last modified: 09 Jan 2021 00:48 by Robin Getz

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