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This document presents the steps to setup an environment for using the EVAL-AD5541ASDZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD5541ASDZ Evaluation Board with the Xilinx KC705 board.
For component evaluation and performance purposes, as opposed to quick prototyping, the user is directed to use the part evaluation setup. This consists of:
The SDP-B controller board is part of Analog Devices System Demonstration Platform (SDP). It provides a high speed USB 2.0 connection from the PC to the component evaluation board. The PC runs the evaluation software. Each evaluation board, which is an SDP compatible daughter board, includes the necessary installation file required for performance testing.
Note: it is expected that the analog performance on the two platforms may differ.
Below is presented a picture of SDP-B Controller Board with the EVAL-AD5541ASDZ Evaluation Board.
The AD5541A is a single, 16-bit, serial input, unbuffered voltage output digital-to-analog converter (DAC) that operates from a single 2.7 V to 5.5 V supply. The DAC output range extends from 0 V to VREF and is guaranteed monotonic, providing ±1 LSB INL accuracy at 16 bits without adjustment over the full specified temperature range of -40°C to +125°C. Offering unbuffered outputs, the AD5541A achieves a 1 µs settling time with low power consumption and low offset errors. Providing low noise performance of 11.8 nV/vHz and low glitch, the AD5541A is suitable for deployment across multiple end systems. The AD5541A uses a versatile 3-wire interface that is compatible with 50 MHz SPI, QSPI™, MICROWIRE™, and DSP interface standards.
The EVAL-AD5541ASDZ evaluation board is designed to help customers quickly prototype new AD5541A circuits and reduce design time.
The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the reference project.
Before connecting the ADI evaluation board to the Xilinx KC705 make sure that the VADJ_FPGA voltage of the KC705 is set to 3.3V. For more details on how to change the setting for VADJ_FPGA visit the Xilinx KC705 product page.
For a quick start evaluation, run the download.bat script located in the SDK/SDK_Workspace/bin folder provided within the Reference Design Files. This script uses XMD to program the FPGA with the HDL Reference Design and download the Software Reference Design into the DDR.
The download.bat script assumes that the Xilinx ISE Design Suite 14.6 is installed at this path: C:/Xilinx/14.6. If the installation path on your computer is different, please modify the script accordingly.
If programming was successful, you should be seeing the command messages appear on the terminal.
The following commands were implemented in this version of EVAL-AD5541A reference project for Xilinx KC705 FPGA board.
|help?||Displays all available commands.|
|voltage=|| Sets the DAC output voltage. Accepted values:
0 .. 2500 - desired output voltage in milivolts.
|voltage?||Displays last written voltage value to the DAC.|
|register=|| Writes to the DAC register. Accepted values:
0 .. 65535 - the value written to the DAC.
|register?||Displays last written value in the DAC register.|
Commands can be executed using a serial terminal connected to the UART peripheral of Xilinx KC705 FPGA.
The hardware platform for each reference projects with FMC-SDP interposer and KC705 evaluation board is common. The next steps should be followed to recreate the software project of the reference design: