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resources:fpga:xilinx:hints:pcore_register_map [04 Mar 2015 10:46] – [AXI DMAC] Lars-Peter Clausenresources:fpga:xilinx:hints:pcore_register_map [13 Apr 2016 17:07] (current) – [HDMI Transmit (axi_hdmi_tx)] Andrei Grozav
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 | | |[0] |RSTN |RW |Reset, a common reset is used for all the interface modules, The default is reset (0x0), software must write 0x1 to bring up the core. | | | |[0] |RSTN |RW |Reset, a common reset is used for all the interface modules, The default is reset (0x0), software must write 0x1 to bring up the core. |
 ^0x0011 ^0x0044 ^REG_CNTRL ^^^HDMI Interface Control & Status ^ ^0x0011 ^0x0044 ^REG_CNTRL ^^^HDMI Interface Control & Status ^
-| | |[1] |FULL_RANGE |RW |If clear (0x0), RGB data is limited to 0x10 to 0xeb. | +| | |[1] |FULL_RANGE |RW |If clear (0x0), color data is limited between the values set in REG_CLIPP_MAX and REG_CLIPP_MIN registers. | 
-|::: |::: |[0] |CSC_BYPASS |RW |If set (0x1) bypasses color space conversion (if equipped). |+|::: |::: |[0] |CSC_BYPASS |RW |If set (0x1) bypasses color space conversion (if equipped). And depending on its value, the default value of color space boundaries is set in the REG_CLIPP_MAX and REG_CLIPP_MIN registers. |
 ^0x0012 ^0x0048 ^REG_CNTRL ^^^HDMI Interface Control & Status ^ ^0x0012 ^0x0048 ^REG_CNTRL ^^^HDMI Interface Control & Status ^
 | | |[1:0] |SOURCE_SEL |RW |Select the HDMI data source- register constant (0x3), incr-pattern (0x2), input (0x1) or disabled (0x0). | | | |[1:0] |SOURCE_SEL |RW |Select the HDMI data source- register constant (0x3), incr-pattern (0x2), input (0x1) or disabled (0x0). |
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 | | |[1] |HDMI_TPM_OOS |RW1C |If set, indicates TPM OOS at the HDMI interface. | | | |[1] |HDMI_TPM_OOS |RW1C |If set, indicates TPM OOS at the HDMI interface. |
 |::: |::: |[0] |VDMA_TPM_OOS |RW1C |If set, indicates TPM OOS at the VDMA interface. | |::: |::: |[0] |VDMA_TPM_OOS |RW1C |If set, indicates TPM OOS at the VDMA interface. |
 +^0x001a ^0x0068 ^REG_CLIPP_MAX ^^^HDMI Interface Control & Status ^
 +| | |[23:16] |R_MAX/Cr_MAX |RW |Defines the maximum value for clipping the red or red-difference chroma component. Default value are 0xf0 for red-difference chroma and 0xfe for red. |
 +|::: |::: |[16:8] |G_MAX/Y_MAX |RW |Defines the maximum value for clipping the green or luma component.  Default values are 0xeb for luma and and 0xfe for green.  |
 +|::: |::: |[7:0] |B_MAX/Cb_MAX |RW |Defines the maximum value for clipping the blue or blue-difference chroma component. Default value are 0xf0 for blue-difference chroma and 0xfe for blue. |
 +^0x001b ^0x006c ^REG_CLIPP_MIN ^^^HDMI Interface Control & Status ^
 +| | |[23:16] |R_MIN/Cr_MIN |RW |Defines the minimum value for clipping the red or red-difference chroma component. Default value are 0x10 for red-difference chroma and 0x01 for red. |
 +|::: |::: |[16:8] |G_MIN/Y_MIN |RW |Defines the minimum value for clipping the green or luma component. Default values are 0x10 for luma and and 0x01 for green.  |
 +|::: |::: |[7:0] |B_MIN/Cb_MIN |RW |Defines the minimum value for clipping the blue or blue-difference chroma component. Default value are 0x10 for blue-difference chroma and 0x01 for blue. |
 ^0x0100 ^0x0400 ^REG_HSYNC_1 ^^^HDMI Interface Control & Status ^ ^0x0100 ^0x0400 ^REG_HSYNC_1 ^^^HDMI Interface Control & Status ^
 | | |[31:16] |H_LINE_ACTIVE[15:0] |RW |This is the horizontal line active pixel width (active resolution length). e.g. 1920 (1080p) | | | |[31:16] |H_LINE_ACTIVE[15:0] |RW |This is the horizontal line active pixel width (active resolution length). e.g. 1920 (1080p) |
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 | | |[31:16] |V_ENABLE_MAX[15:0] |RW |This is the vertical data enable maximum. It is the sum of V_ENABLE_MIN and the active pixel height. e.g. 1121 (41 + 1080) (1080p) | | | |[31:16] |V_ENABLE_MAX[15:0] |RW |This is the vertical data enable maximum. It is the sum of V_ENABLE_MIN and the active pixel height. e.g. 1121 (41 + 1080) (1080p) |
 |::: |::: |[15:0] |V_ENABLE_MIN[15:0] |RW |This is the vertical data enable minimum. It is the sum of vertical back porch (number of lines between the falling edge of VSYNC to the rising edge of DE) and the sync width. e.g. 41 (36 + 5) (1080p) | |::: |::: |[15:0] |V_ENABLE_MIN[15:0] |RW |This is the vertical data enable minimum. It is the sum of vertical back porch (number of lines between the falling edge of VSYNC to the rising edge of DE) and the sync width. e.g. 41 (36 + 5) (1080p) |
-^Tue Nov 26 10:04:57 2013 ^^^^^^ +^Wed Apr 13 17:59:19 2016 ^^^^^^
  
 ==== Clock Generator ==== ==== Clock Generator ====
resources/fpga/xilinx/hints/pcore_register_map.txt · Last modified: 13 Apr 2016 17:07 by Andrei Grozav

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