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FPGA Reference Designs: PCORE Register Map

Overview

The table below lists the common register map used by all the device pcores in the reference designs. All the registers are dword based and do not support byte addressing. That is, a read at byte address 0x01, 0x02 or 0x03 all return the register at byte address 0x00. The registers are grouped as per functionality, any exceptions may be noted on the specific pcore documentation.

OBSOLETE: This register map is applicable only to the ISE/XPS older designs. The latest register map is here http://wiki.analog.com/resources/fpga/docs/hdl/regmap

Register Map

General

Address Bits Name Type Description
DWORD BYTE
0x0000 0x0000 REG_VERSION Version and Scratch Registers
[31:0] VERSION[31:0] RO Version number.
0x0001 0x0004 REG_ID Version and Scratch Registers
[31:0] ID[31:0] RO Instance identifier number.
0x0002 0x0008 REG_SCRATCH Version and Scratch Registers
[31:0] SCRATCH[31:0] RW Scratch register.
Tue Nov 26 10:04:57 2013

ADC Common

Address Bits Name Type Description
DWORD BYTE
0x0010 0x0040 REG_RSTN ADC Interface Control & Status
[1] MMCM_RSTN RW MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
[0] RSTN RW Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x0011 0x0044 REG_CNTRL ADC Interface Control & Status
[2] R1_MODE RW Select number of RF channels 1 (0x1) or 2 (0x0).
[1] DDR_EDGESEL RW Select rising edge (0x0) or falling edge (0x1) for the first part of a sample (if applicable) followed by the successive edges for the remaining parts. This only controls how the sample is delineated from the incoming data post DDR registers.
[0] PIN_MODE RW Select interface pin mode to be clock multiplexed (0x1) or pin multiplexed (0x0). In clock multiplexed mode, samples are received on alternative clock edges. In pin multiplexed mode, samples are interleaved or grouped on the pins at the same clock edge.
0x0015 0x0054 REG_CLK_FREQ ADC Interface Control & Status
[31:0] CLK_FREQ[31:0] RO Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016 0x0058 REG_CLK_RATIO ADC Interface Control & Status
[31:0] CLK_RATIO[31:0] RO Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0017 0x005c REG_STATUS ADC Interface Control & Status
[3] PN_ERR RO If set, indicates pn error in one or more channels.
[2] PN_OOS RO If set, indicates pn oos in one or more channels.
[1] OVER_RANGE RO If set, indicates over range in one or more channels.
[0] STATUS RO Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018 0x0060 REG_DELAY_CNTRL ADC Interface Control & Status
[17] DELAY_SEL RW Delay select, a 0x0 to 0x1 transition in this register initiates a delay access controlled by the registers below.
[16] DELAY_RWN RW Delay read (0x1) or write (0x0), the delay is accessed directly (no increment or decrement) with an address corresponding to each pin, and data corresponding to the total delay.
[15:8] DELAY_ADDRESS[7:0] RW Delay address, the range depends on the interface pins, data pins are usually at the lower range.
[4:0] DELAY_WDATA[4:0] RW Delay write data, a value of 1 corresponds to (1/200)ns for most devices.
0x0019 0x0064 REG_DELAY_STATUS ADC Interface Control & Status
[9] DELAY_LOCKED RO Indicates delay locked (0x1) state. If this bit is read 0x0, delay control has failed to calibrate the elements.
[8] DELAY_STATUS RO If set, indicates busy status (access pending). The read data may not be valid if this bit is set.
[4:0] DELAY_RDATA[4:0] RO Delay read data, current delay value in the elements
0x001c 0x0070 REG_DRP_CNTRL ADC Interface Control & Status
[28] DRP_RWN RW DRP read (0x1) or write (0x0) select (does not include GTX lanes).
[27:16] DRP_ADDRESS[11:0] RW DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes).
[15:0] DRP_WDATA[15:0] RW DRP write data (does not include GTX lanes).
0x001d 0x0074 REG_DRP_STATUS ADC Interface Control & Status
[16] DRP_STATUS RO If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes).
[15:0] DRP_RDATA RO DRP read data (does not include GTX lanes).
0x0022 0x0088 REG_UI_STATUS User Interface Status
[2] UI_OVF RW1C User Interface overflow. If set, indicates an overflow occured during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
[1] UI_UNF RW1C User Interface underflow. If set, indicates an underflow occured during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
[0] UI_RESERVED RW1C Reserved for backward compatibility.
0x0028 0x00a0 REG_USR_CNTRL_1 ADC Interface Control & Status
[7:0] USR_CHANMAX[7:0] RW This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules post data capture as another input to this common multiplexer. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
0x0030 0x00c0 REG_USR_CNTRL_1 ADC Interface Control & Status
[0] ADC_DP_DISABLE RO This indicates the data path disable setting of this pcore. If disabled, most of the HDL data path modules are disabled allowing an external core full access to the raw ADC data.
Tue Nov 26 10:04:57 2013

ADC Channel

Address Bits Name Type Description
DWORD BYTE
0x0100 0x0400 REG_CHAN_CNTRL ADC Interface Control & Status
[10] PN_SEL RW if set, enables an additional PN sequence monitor (shares same status signals).
[9] IQCOR_ENB RW if set, enables IQ correction. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
[8] DCFILT_ENB RW if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
[6] FORMAT_SIGNEXT RW if set, enables sign extension (applicable only in 2's complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
[5] FORMAT_TYPE RW Select offset binary (0x1) or 2's complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
[4] FORMAT_ENABLE RW Enable data format conversion (see register bits above). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
[1] PN_TYPE RW Selects PN type PN9 (0x0) or PN23 (0x1). If software is changing this bit, the OOS/ERR registers must be cleared before checking status again.
[0] ENABLE RW If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
0x0101 0x0404 REG_CHAN_STATUS ADC Interface Control & Status
[2] PN_ERR RW1C PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared.
[1] PN_OOS RW1C PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern.
[0] OVER_RANGE RW1C If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards.
0x0104 0x0410 REG_CHAN_CNTRL_1 ADC Interface Control & Status
[31:16] DCFILT_OFFSET[15:0] RW DC removal (if equipped) offset. This is a 2's complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
[15:0] DCFILT_COEFF[15:0] RW DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
0x0105 0x0414 REG_CHAN_CNTRL_2 ADC Interface Control & Status
[31:16] IQCOR_COEFF_1[15:0] RW IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
[15:0] IQCOR_COEFF_2[15:0] RW IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
0x0108 0x0420 REG_CHAN_USR_CNTRL_1 ADC Interface Control & Status
[25] USR_DATATYPE_BE RW The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
[24] USR_DATATYPE_SIGNED RW The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
[23:16] USR_DATATYPE_SHIFT[7:0] RW The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
[15:8] USR_DATATYPE_TOTAL_BITS[7:0] RW The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
[7:0] USR_DATATYPE_BITS[7:0] RW The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
0x0109 0x0424 REG_CHAN_USR_CNTRL_2 ADC Interface Control & Status
[31:16] USR_DECIMATION_M[15:0] RW This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The toal decimation factor is of the form M/N. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
[15:0] USR_DECIMATION_N[15:0] RW This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The toal decimation factor is of the form M/N. NOT-APPLICABLE if ADC_DP_DISABLE is set (0x1).
0x0110 0x0440 REG_* Channel 1, similar to register 0x100 to 0x10f.
0x0120 0x0480 REG_* Channel 2, similar to register 0x100 to 0x10f.
0x01f0 0x07c0 REG_* Channel 15, similar to register 0x100 to 0x10f.
Tue Nov 26 10:04:57 2013

DAC Common

Address Bits Name Type Description
DWORD BYTE
0x1010 0x4040 REG_RSTN DAC Interface Control & Status
[1] MMCM_RSTN RW MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
[0] RSTN RW Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x1011 0x4044 REG_CNTRL_1 DAC Interface Control & Status
[0] ENABLE RW A 0 to 1 transition enables all the data channels.
0x1012 0x4048 REG_CNTRL_2 DAC Interface Control & Status
[7] PAR_TYPE RW Select parity even (0x0) or odd (0x1).
[6] PAR_ENB RW Select parity (0x1) or frame (0x0) mode.
[5] R1_MODE RW Select number of RF channels 1 (0x1) or 2 (0x0).
[4] DATA_FORMAT RW Select data format 2's complement (0x0) or offset binary (0x1). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
[3:0] DATA_SEL[3:0] RW Select dds (4'h0), sed (4'h01) or ddr (4'h02) as dac data.
0x1013 0x404c REG_RATECNTRL DAC Interface Control & Status
[7:0] RATE[7:0] RW The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock.
0x1014 0x4050 REG_FRAME DAC Interface Control & Status
[0] FRAME RW The use of frame is device specific. Usually a 0 → 1 transition generates a FRAME (1 DCI clock period) pulse on the interface.
0x1015 0x4054 REG_STATUS DAC Interface Control & Status
[31:0] CLK_FREQ[31:0] RO Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x1016 0x4058 REG_STATUS DAC Interface Control & Status
[31:0] CLK_RATIO[31:0] RO Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x1017 0x405c REG_STATUS DAC Interface Control & Status
[0] STATUS RO Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x101c 0x4070 REG_DRP_CNTRL DRP Control & Status
[28] DRP_RWN RW DRP read (0x1) or write (0x0) select (does not include GTX lanes).
[27:16] DRP_ADDRESS[11:0] RW DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes).
[15:0] DRP_WDATA[15:0] RW DRP write data (does not include GTX lanes).
0x101d 0x4074 REG_DRP_STATUS DAC Interface Control & Status
[16] DRP_STATUS RO If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes).
[15:0] DRP_RDATA RO DRP read data (does not include GTX lanes).
0x1022 0x4088 REG_UI_STATUS User Interface Status
[1] UI_OVF RW1C User Interface overflow. If set, indicates an overflow occured during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
[0] UI_UNF RW1C User Interface underflow. If set, indicates an underflow occured during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
0x1028 0x40a0 REG_USR_CNTRL_1 DAC User Control & Status
[7:0] USR_CHANMAX[7:0] RW This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
0x0030 0x00c0 REG_USR_CNTRL_1 DAC Interface Control & Status
[0] DAC_DP_DISABLE RO This indicates the data path disable setting of this pcore. If disabled, most of the HDL data path modules are disabled allowing an external core full access to the raw DAC data.
Tue Nov 26 10:04:57 2013

DAC Channel

Address Bits Name Type Description
DWORD BYTE
0x1100 0x4400 REG_CHAN_CNTRL_1 DAC Channel Control & Status (channel - 0)
[3:0] DDS_SCALE_1[3:0] RW The DDS scale for tone 1. The DDS for a channel consists of two tones. The final output is (channel_1 « scale_1) + (channel_2 « scale_2) NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
0x1101 0x4404 REG_CHAN_CNTRL_2 DAC Channel Control & Status (channel - 0)
[31:16] DDS_INIT_1[15:0] RW The DDS phase initialization for tone 1. The DDS for a channel consists of two tones. The final output is (channel_1 « scale_1) + (channel_2 « scale_2) NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
[15:0] DDS_INCR_1[15:0] RW The DDS phase increment for tone 1. The DDS for a channel consists of two tones. The final output is (channel_1 « scale_1) + (channel_2 « scale_2) NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
0x1102 0x4408 REG_CHAN_CNTRL_3 DAC Channel Control & Status (channel - 0)
[3:0] DDS_SCALE_2[3:0] RW The DDS scale for tone 2. The DDS for a channel consists of two tones. The final output is (channel_1 « scale_1) + (channel_2 « scale_2) NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
0x1103 0x440c REG_CHAN_CNTRL_4 DAC Channel Control & Status (channel - 0)
[31:16] DDS_INIT_2[15:0] RW The DDS phase initialization for tone 2. The DDS for a channel consists of two tones. The final output is (channel_1 « scale_1) + (channel_2 « scale_2) NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
[15:0] DDS_INCR_2[15:0] RW The DDS phase increment for tone 2. The DDS for a channel consists of two tones. The final output is (channel_1 « scale_1) + (channel_2 « scale_2) NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
0x1104 0x4410 REG_CHAN_CNTRL_5 DAC Channel Control & Status (channel - 0)
[31:16] DDS_PATT_2[15:0] RW The DDS data pattern for this channel.
[15:0] DDS_PATT_1[15:0] RW The DDS data pattern for this channel.
0x1105 0x4414 REG_CHAN_CNTRL_6 DAC Channel Control & Status (channel - 0)
[1] DAC_LB_ENB RW If set enables loopback of receive data (applicable only on shared interface).
[0] DAC_PN_ENB RW If set enables PN sequence (DATA_SEL[3:0] must be set to 0x1).
0x1108 0x4420 REG_USR_CNTRL_3 DAC Channel Control & Status (channel - 0)
[25] USR_DATATYPE_BE RW The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
[24] USR_DATATYPE_SIGNED RW The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
[23:16] USR_DATATYPE_SHIFT[7:0] RW The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
[15:8] USR_DATATYPE_TOTAL_BITS[7:0] RW The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
[7:0] USR_DATATYPE_BITS[7:0] RW The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
0x1109 0x4424 REG_USR_CNTRL_4 DAC Channel Control & Status (channel - 0)
[31:16] USR_INTERPOLATION_M[15:0] RW This holds the user interpolation M value of the channel that is currently being selected on the multiplexer above. The toal interpolation factor is of the form M/N. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
[15:0] USR_INTERPOLATION_N[15:0] RW This holds the user interpolation N value of the channel that is currently being selected on the multiplexer above. The toal interpolation factor is of the form M/N. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
0x1110 0x4440 REG_* Channel 1, similar to registers 0x100 to 0x10f.
0x1120 0x4480 REG_* Channel 2, similar to registers 0x100 to 0x10f.
0x11f0 0x47c0 REG_* Channel 15, similar to registers 0x100 to 0x10f.
Tue Nov 26 10:04:57 2013

JESD Receive

Address Bits Name Type Description
DWORD BYTE
0x0010 0x0040 REG_RSTN JESD General Control & Status
[3] DRP_RSTN RW DRP Reset Only. Reset, default is IN-RESET (0x0), software must write a 0x1 to bring up the interface.
[2] IP_RSTN RW IP Reset Only. Reset, default is IN-RESET (0x0), software must write a 0x1 to bring up the interface.
[1] IP_RSTN RW Core Reset Only (non-IP). Reset, default is IN-RESET (0x0), software must write a 0x1 to bring up the interface.
[0] GT_RSTN RW GT Reset Only (PLL, PMA and PCS -within the GTX). Reset, default is IN-RESET (0x0), software must write a 0x1 to bring up the interface.
0x0011 0x0044 REG_SYSREF JESD General Control & Status
[1] IP_SYSREF RW A 0 to 1 transition generates a SYSREF pulse for the XIP.
[0] SYSREF RW A 0 to 1 transition generates a SYSREF pulse on the interface.
0x0012 0x0048 REG_SYNC JESD General Control & Status
[0] SYNC RW The SYNC output is deasserted if this bit and hardware are both set.
0x0014 0x0050 REG_RX_CNTRL_1 JESD Receive Control & Status
[18] RX_LANESYNC_ENB RW Receive lane synchronization enable.
[17] RX_DESCR_ENB RW Receive descrambler enable.
[16] RX_SYSREF_ENB RW Receive SYESREF enable.
[15:8] RX_MFRM_FRMCNT[7:0] RW Receive mult-frame frame count, set to one less than the number of frames in a multi-frame.
[7:0] RX_FRM_BYTECNT[7:0] RW Receive frame byte count, set to one less than the number of bytes in a frame.
0x0015 0x0054 REG_RX_CNTRL_2 JESD Receive Control & Status
[20] RX_ERRRPT_DISB RW Receive error reporting disable.
[19:16] RX_TESTMODE[3:0] RW Receive test mode.
[15:0] RX_BUFDELAY[15:0] RW Receive buffer delay.
0x0017 0x005c REG_RX_LANESEL JESD, Lane Control & Status
[7:0] RX_LANESEL[7:0] RW Receive lane select, lane information, DRP access and eye scan are per lane and this register selects the lane.
0x0018 0x0060 REG_RX_STATUS JESD, Lane Control & Status
[0] RX_STATUS RO Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0019 0x0064 REG_RX_INIT_DATA_0 JESD, Lane Control & Status
[31:0] RX_INIT_DATA_0[31:0] RO Receive lane information (collected during ILAS phase).
0x001a 0x0068 REG_RX_INIT_DATA_1 JESD, Lane Control & Status
[31:0] RX_INIT_DATA_1[31:0] RO Receive lane information (collected during ILAS phase).
0x001b 0x006c REG_RX_INIT_DATA_2 JESD, Lane Control & Status
[31:0] RX_INIT_DATA_2[31:0] RO Receive lane information (collected during ILAS phase).
0x001c 0x0070 REG_RX_INIT_DATA_2 JESD, Lane Control & Status
[31:0] RX_INIT_DATA_3[31:0] RO Receive lane information (collected during ILAS phase).
0x001d 0x0074 REG_RX_BUFCNT JESD, Lane Control & Status
[7:0] RX_BUFCNT[7:0] RO Receive lane alignment buffer count.
0x001e 0x0078 REG_RX_TEST_MFCNT JESD, Lane Control & Status
[31:0] RX_TEST_MFCNT[31:0] RO Receive test multi-frame count.
0x001f 0x007c REG_RX_TEST_ILACNT JESD, Lane Control & Status
[31:0] RX_TEST_ILACNT[31:0] RO Receive test ILAS count.
0x0020 0x0080 REG_RX_TEST_ERRCNT JESD, Lane Control & Status
[31:0] RX_TEST_ERRCNT[31:0] RO Receive test error count.
0x0024 0x0090 REG_DRP_CNTRL JESD, GT DRP Control & Status
[28] DRP_RWN RW DRP read (0x1) or write (0x0) select.
[27:16] DRP_ADDRESS[11:0] RW DRP address.
[15:0] DRP_WDATA[15:0] RW DRP write data.
0x0025 0x0094 REG_DRP_STATUS JESD, Lane Control & Status
[16] DRP_STATUS RO If set indicates busy (access pending). The read data may not be valid if this bit is set.
[15:0] DRP_RDATA RO DRP read data.
0x0028 0x00a0 REG_EYESCAN_CNTRL JESD, GT Eye Scan Control & Status
[2] EYESCAN_INIT RW Eye scan init - if set, enables initialization of GT. It can be disabled on successive eye scan.
[1] EYESCAN_STOP RW Eye scan stop- a 0x0 to 0x1 transition terminates eye scan on the selected lane.
[0] EYESCAN_START RW Eye scan start- a 0x0 to 0x1 transition initiates eye scan on the selected lane. The scan might take a while, software must monitor the status.
0x0029 0x00a4 REG_EYESCAN_PRESCALE JESD, Lane Control & Status
[4:0] EYESCAN_PRESCALE[4:0] RW Eye scan prescale, refer to the Xilinx documentation for details - the counters are prescaled to 2(n+1).
0x002a 0x00a8 REG_EYESCAN_VOFFSET JESD, Lane Control & Status
[23:16] EYESCAN_VOFFSET_STEP[7:0] RW Eye scan vertical offset step. The value must be set in 2's complement, refer to the Xilinx documentation for details.
[15:8] EYESCAN_VOFFSET_MAX[7:0] RW Eye scan vertical offset maximum (+128). The value must be set in 2's complement, refer to the Xilinx documentation for details.
[7:0] EYESCAN_VOFFSET_MIN[7:0] RW Eye scan vertical offset minimum (-128). The value must be set in 2's complement, refer to the Xilinx documentation for details.
0x002b 0x00ac REG_EYESCAN_HOFFSET_1 JESD, Lane Control & Status
[27:16] EYESCAN_HOFFSET_MAX[11:0] RW Eye scan horizontal offset maximum. The value depends on the clock divider, as the eye scan is post CDR and comparison happens on parallel bus. The value must be set in 2's complement, refer to the Xilinx documentation for details.
[11:0] EYESCAN_HOFFSET_MIN[11:0] RW Eye scan horizontal offset minimum. The value depends on the clock divider, as the eye scan is post CDR and comparison happens on parallel bus. The value must be set in 2's complement, refer to the Xilinx documentation for details.
0x002c 0x00b0 REG_EYESCAN_HOFFSET_2 JESD, Lane Control & Status
[11:0] EYESCAN_HOFFSET_STEP[11:0] RW Eye scan horizontal offset step. The value must be set in 2's complement, refer to the Xilinx documentation for details.
0x002d 0x00b4 REG_EYESCAN_DMA_STARTADDR JESD, Lane Control & Status
[31:0] EYESCAN_DMA_STARTADDR[31:0] RW Eye scan DMA start address. The AXI master interface writes eye scan data starting at this address. The first data written corresponds to the minimum of horizontal and vertical offsets (UT = 0).
0x002e 0x00b8 REG_EYESCAN_SDATA_1_0 JESD, Lane Control & Status
[31:16] EYESCAN_SDATA1[15:0] RW Eye scan sample data mask word (1) (80bits = {4, 3, 2, 1, 0})
[15:0] EYESCAN_SDATA0[15:0] RW Eye scan sample data mask word (0) (80bits = {4, 3, 2, 1, 0})
0x002f 0x00bc REG_EYESCAN_SDATA_3_2 JESD, Lane Control & Status
[31:16] EYESCAN_SDATA3[15:0] RW Eye scan sample data mask word (3) (80bits = {4, 3, 2, 1, 0})
[15:0] EYESCAN_SDATA2[15:0] RW Eye scan sample data mask word (2) (80bits = {4, 3, 2, 1, 0})
0x0030 0x00c0 REG_EYESCAN_SDATA_4 JESD, Lane Control & Status
[15:0] EYESCAN_SDATA4[15:0] RW Eye scan sample data mask word (0) (80bits = {4, 3, 2, 1, 0})
0x0031 0x00c4 REG_EYESCAN_QDATA_1_0 JESD, Lane Control & Status
[31:16] EYESCAN_QDATA1[15:0] RW Eye scan qualifier data mask word (1) (80bits = {4, 3, 2, 1, 0})
[15:0] EYESCAN_QDATA0[15:0] RW Eye scan qualifier data mask word (0) (80bits = {4, 3, 2, 1, 0})
0x0032 0x00c8 REG_EYESCAN_QDATA_3_2 JESD, Lane Control & Status
[31:16] EYESCAN_QDATA3[15:0] RW Eye scan qualifier data mask word (3) (80bits = {4, 3, 2, 1, 0})
[15:0] EYESCAN_QDATA2[15:0] RW Eye scan qualifier data mask word (2) (80bits = {4, 3, 2, 1, 0})
0x0033 0x00cc REG_EYESCAN_QDATA_4 JESD, Lane Control & Status
[15:0] EYESCAN_QDATA4[15:0] RW Eye scan qualifier data mask word (0) (80bits = {4, 3, 2, 1, 0})
0x0038 0x00e0 REG_EYESCAN_STATUS JESD, Lane Control & Status
[1] EYESCAN_DMAERR RW1C Eye scan DMA error. If set, indicates a target error on AXI bus.
[0] EYESCAN_STATUS RO Eye scan status. If set, indicates the eye scan is running. Software may still access the data at the destination, but it may not be complete until this bit is cleared by hardware.
0x0039 0x00e4 REG_EYESCAN_RATE JESD, Lane Control & Status
[1] EYESCAN_RATE RO Indicates eye scan rate - 0x1 (-32 to +32), 0x2 (-64 to +64), 0x4 (-128 to +128), 0x8 (-256 to +256), 0x10 (-512 to +512).
Tue Nov 26 10:04:57 2013

DDR Controller

Address Bits Name Type Description
DWORD BYTE
0x0010 0x0040 REG_RSTN DDR Interface Control & Status
[0] RSTN RW DDR controller reset, software must write 0x1 to bring up the core.
0x0017 0x005c REG_STATUS DDR Interface Control & Status
[0] STATUS RO Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018 0x0060 REG_DDR_CNTRL DDR Write Control & Status
[1] DDR_STREAM RW If set, DDR write is in stream mode, data is continously passed to the DDR module,
[0] DDR_START RW A 0x0 to 0x1 transition on this bit initiates DDR writes.
0x0019 0x0064 REG_DDR_COUNT DDR Write Control & Status
[31:0] DDR_COUNT[31:0] RW DDR data count, usually the final dma data count (see below) in number of bytes. The software could program the DDR controller with the same DMA settings. The count is based on bytes, however the value must be an integer multiple of the bus width. The value programmed is the actual number of bytes, hence zero is not valid.
0x001a 0x0068 REG_DDR_STATUS DDR Write Control & Status
[2] DDR_OVF RW1C DDR write overflow. If set, indicates an overflow occured during data transfer. Software must write a 0x1 before starting another transfer to clear any left off status from a previous write.
[1] DDR_UNF RW1C DDR write underflow. If set, indicates an underflow occured during data transfer. Software must write a 0x1 before starting another transfer to clear any left off status from a previous write.
[0] DDR_STATUS RW1C DDR write status. If set, indicates access is pending and transfer is not complete.
0x001b 0x006c REG_DDR_BUSWIDTH DDR Write Control & Status
[31:0] DDR_BUSWIDTH RO DDR data bus width in number of bytes (the DDR count must be an integer multiple of this bus width).
0x0020 0x0080 REG_DMA_CNTRL DDR Read Control & Status
[1] DMA_STREAM RW If set, DMA is in stream mode, data is continously passed to the DMA module, with TLAST asserted every DMA count cycles on the data bus. The ADC interface does not do the actual DMA, so the success of a stream mode (bandwidth effects) depends mainly on the DMA module.
[0] DMA_START RW A 0x0 to 0x1 transition on this bit initiates DMA.
0x0021 0x0084 REG_DMA_COUNT DDR Read Control & Status
[31:0] DMA_COUNT[31:0] RW DMA data count, mainly used to assert TLAST. Software must program the DMA controller with the same settings. The count is based on bytes (same as DMA setting), however the value must be an integer multiple of the bus width. In most cases the granularity is 4 bytes. The value programmed is the actual number of bytes, hence zero is not valid.
0x0022 0x0088 REG_DMA_STATUS DDR Read Control & Status
[2] DMA_OVF RW1C DMA overflow. If set, indicates an overflow occured during data transfer. Software must write a 0x1 before starting another transfer to clear any left off status from a previous DMA.
[1] DMA_UNF RW1C DMA underflow. If set, indicates an underflow occured during data transfer. Software must write a 0x1 before starting another transfer to clear any left off status from a previous DMA.
[0] DMA_STATUS RW1C DMA status. If set, indicates access is pending and transfer is not complete.
0x0023 0x008c REG_DMA_BUSWIDTH DDR Read Control & Status
[31:0] DMA_BUSWIDTH RO DMA data bus width in number of bytes (the DMA count must be an integer multiple of this bus width).
Tue Nov 26 10:04:57 2013

HDMI Transmit

Address Bits Name Type Description
DWORD BYTE
0x0010 0x0040 REG_RSTN HDMI Interface Control & Status
[0] RSTN RW Reset, a common reset is used for all the interface modules, The default is reset (0x0), software must write 0x1 to bring up the core.
0x0011 0x0044 REG_CNTRL HDMI Interface Control & Status
[1] FULL_RANGE RW If clear (0x0), RGB data is limited to 0x10 to 0xeb.
[0] CSC_BYPASS RW If set (0x1) bypasses color space conversion (if equipped).
0x0012 0x0048 REG_CNTRL HDMI Interface Control & Status
[1:0] SOURCE_SEL RW Select the HDMI data source- register constant (0x3), incr-pattern (0x2), input (0x1) or disabled (0x0).
0x0013 0x004c REG_CNTRL HDMI Interface Control & Status
[23:0] CONST_RGB[23:0] RW This is the RGB value transmitted, if the source is constant (see above).
0x0015 0x0054 REG_CLK_FREQ HDMI Interface Control & Status
[31:0] CLK_FREQ[31:0] RO Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016 0x0058 REG_CLK_RATIO HDMI Interface Control & Status
[31:0] CLK_RATIO[31:0] RO Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0017 0x005c REG_STATUS ADC Interface Control & Status
[0] STATUS RO Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018 0x0060 REG_VDMA_STATUS HDMI Interface Control & Status
[1] VDMA_OVF RW1C If set, indicates vdma overflow.
[0] VDMA_UNF RW1C If set, indicates vdma underflow.
0x0019 0x0064 REG_TPM_STATUS HDMI Interface Control & Status
[1] HDMI_TPM_OOS RW1C If set, indicates TPM OOS at the HDMI interface.
[0] VDMA_TPM_OOS RW1C If set, indicates TPM OOS at the VDMA interface.
0x0100 0x0400 REG_HSYNC_1 HDMI Interface Control & Status
[31:16] H_LINE_ACTIVE[15:0] RW This is the horizontal line active pixel width (active resolution length). e.g. 1920 (1080p)
[15:0] H_LINE_WIDTH[15:0] RW This is the horizontal line width (no. of pixel clocks per line). e.g. 2200 (1080p)
0x0101 0x0404 REG_HSYNC_2 HDMI Interface Control & Status
[15:0] H_SYNC_WIDTH[15:0] RW This is the horizontal sync width (no. of pixel clocks). e.g. 44 (1080p)
0x0102 0x0408 REG_HSYNC_3 HDMI Interface Control & Status
[31:16] H_ENABLE_MAX[15:0] RW This is the horizontal data enable maximum. It is the sum of H_ENABLE_MIN and the active pixel width. e.g. 2112 (192 + 1920) (1080p)
[15:0] H_ENABLE_MIN[15:0] RW This is the horizontal data enable minimum. It is the sum of horizontal back porch (number of clock cycles between the falling edge of HSYNC to the rising edge of DE) and the sync width. e.g. 192 (44 + 148) (1080p)
0x0110 0x0440 REG_VSYNC_1 HDMI Interface Control & Status
[31:16] V_FRAME_ACTIVE[15:0] RW This is the vertical frame active line width (active resolution height). e.g. 1080 (1080p)
[15:0] V_FRAME_WIDTH[15:0] RW This is the vertical frame width (no. of lines per frame). e.g. 1125 (1080p)
0x0111 0x0444 REG_VSYNC_2 HDMI Interface Control & Status
[15:0] V_SYNC_WIDTH[15:0] RW This is the vertical sync width (no. of lines). e.g. 5 (1080p)
0x0112 0x0448 REG_VSYNC_3 HDMI Interface Control & Status
[31:16] V_ENABLE_MAX[15:0] RW This is the vertical data enable maximum. It is the sum of V_ENABLE_MIN and the active pixel height. e.g. 1121 (41 + 1080) (1080p)
[15:0] V_ENABLE_MIN[15:0] RW This is the vertical data enable minimum. It is the sum of vertical back porch (number of lines between the falling edge of VSYNC to the rising edge of DE) and the sync width. e.g. 41 (36 + 5) (1080p)
Tue Nov 26 10:04:57 2013

Clock Generator

Address Bits Name Type Description
DWORD BYTE
0x0010 0x0040 REG_RSTN Interface Control & Status
[1] MMCM_RSTN RW MMCM reset (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
[0] RSTN RW Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x0017 0x005c REG_STATUS ADC Interface Control & Status
[0] STATUS RO Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x001c 0x0070 REG_DRP_CNTRL ADC Interface Control & Status
[28] DRP_RWN RW DRP read (0x1) or write (0x0) select (does not include GTX lanes).
[27:16] DRP_ADDRESS[11:0] RW DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes).
[15:0] DRP_WDATA[15:0] RW DRP write data (does not include GTX lanes).
0x001d 0x0074 REG_DRP_STATUS ADC Interface Control & Status
[16] DRP_STATUS RO If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes).
[15:0] DRP_RDATA RO DRP read data (does not include GTX lanes).
Tue Nov 26 10:04:57 2013

FFT Common

Address Bits Name Type Description
DWORD BYTE
0x0010 0x0040 REG_RSTN FFT Interface Control & Status
[0] RSTN RW Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x0011 0x0044 REG_CNTRL FFT Interface Control & Status
[31:0] CFG_DATA[31:0] RW The configuration data is passed as it is to the FFT core. The format is dependent on the Xilinx's IP core.
0x0012 0x0048 REG_CNTRL FFT Interface Control & Status
[16] ENABLE RW The H. window enable (requires 0→1 transition).
[15:0] INCR[15:0] RW This is the window phase increment function - cos(phase).
0x0017 0x005c REG_STATUS FFT Interface Control & Status
[0] STATUS RO Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018 0x0060 REG_STATUS FFT Interface Control & Status
[19:0] STATUS RW1C The FFT status is passed to the software through this register. The fields are controlled by the Xilinx's IP core.
Tue Nov 26 10:04:57 2013

AXIS Receive

Address Bits Name Type Description
DWORD BYTE
0x0010 0x0040 REG_RSTN AXIS Interface Control & Status
[0] RSTN RW Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x0020 0x0080 REG_DMA_CNTRL AXIS Interface Control & Status
[1] DMA_STREAM RW If set, DMA is in stream mode, data is continously passed to the DMA module, with TLAST asserted every DMA count cycles on the data bus. The ADC interface does not do the actual DMA, so the success of a stream mode (bandwidth effects) depends mainly on the DMA module.
[0] DMA_START RW A 0x0 to 0x1 transition on this bit initiates DMA.
0x0021 0x0084 REG_DMA_COUNT AXIS Interface Control & Status
[31:0] DMA_COUNT[31:0] RW DMA data count, mainly used to assert TLAST. Software must program the DMA controller with the same settings. The count is based on bytes (same as DMA setting), however the value must be an integer multiple of the bus width. In most cases the granularity is 4 bytes. The value programmed is the actual number of bytes, hence zero is not valid.
0x0022 0x0088 REG_DMA_STATUS AXIS Interface Control & Status
[2] DMA_OVF RW1C DMA overflow. If set, indicates an overflow occured during data transfer. Software must write a 0x1 before starting another transfer to clear any left off status from a previous DMA.
[0] DMA_STATUS RO DMA status. If set, indicates access is pending and transfer is not complete. NOT-APPLICABLE (Moved to new AXIS pcore).
0x0023 0x008c REG_DMA_BUSWIDTH AXIS Interface Control & Status
[31:0] DMA_BUSWIDTH RO DMA data bus width in number of bytes (the DMA count must be an integer multiple of this bus width).
Tue Nov 26 10:04:57 2013

AXIS Transmit

Address Bits Name Type Description
DWORD BYTE
0x1010 0x4040 REG_RSTN AXIS Interface Control & Status
[0] RSTN RW Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x1021 0x4084 REG_VDMA_FRMCNT VDMA Control & Status
[31:0] VDMA_FRMCNT[31:0] RW This register controls the frame sync assertion to VDMA. This can be set to any count greater than the actual frame length (in bytes).
0x1022 0x4088 REG_VDMA_STATUS VDMA Interface Control & Status
[1] VDMA_OVF RW1C VDMA overflow. If set, indicates an overflow occured during data transfer. Software must write a 0x1 before starting another transfer to clear any left off status from a previous VDMA.
[0] VDMA_UNF RW1C VDMA underflow. If set, indicates an underflow occured during data transfer. Software must write a 0x1 before starting another transfer to clear any left off status from a previous VDMA.
Tue Nov 26 10:04:57 2013

AXI DMAC

Address Bits Name Type Description
DWORD BYTE
0x020 0x0080 IRQ_MASK AXI DMA Controller
[1] END_OF_TRANSFER RW Masks the END_OF_TRANSFER IRQ.
[0] START_OF_TRANSFER RW Masks the START_OF_TRANSFER IRQ.
0x021 0x0084 IRQ_PENDING AXI DMA Controller
[1] END_OF_TRANSFER RW1C This bit will be asserted if a transfer has been completed and the END_OF_TRANSFER bit in the IRQ_MASK register is not set. Either if all bytes have been transferred or an error occurred during the transfer.
[0] START_OF_TRANSFER RW1C This bit will be asserted if a transfer has been successfully queued and it is possible to queue the next transfer and the START_OF_TRANSFER bit in the IRQ_MASK register is not set.
0x022 0x0088 IRQ_SOURCE AXI DMA Controller
[1] END_OF_TRANSFER RW1C This bit will be asserted if a transfer has been completed. Either if all bytes have been transferred or an error occurred during the transfer.
[0] START_OF_TRANSFER RW1C This bit will be asserted if a transfer has been successfully queued and it is possible to queue the next transfer.
0x100 0x0400 CONTROL AXI DMA Controller
[1] PAUSE RW When set to 1 the currently active transfer is paused. It will be resumed once the bit is cleared again.
[0] ENABLE RW When set to 1 the DMA channel is enabled.
0x101 0x0404 TRANSFER_ID AXI DMA Controller
[4:0] TRANSFER_ID RO This register contains the ID of the next transfer. The ID is generated by the DMAC and after the transfer has been started can be used to check if the transfer has finished by checking the corresponding bit in the TRANSFER_DONE register. The contents of this register is only valid if TRANSFER_START is 0.
0x102 0x0408 TRANSFER_START AXI DMA Controller
[0] TRANSFER_START RW Writing a 1 to this register queues a new transfer. The bit transitions back to 0 once the transfer has been successfully queued or the DMA is channel is disabled. Writing a 0 to this register has no effect.
0x103 0x040c FLAGS AXI DMA Controller
[0] CYCLIC RW Setting this field to 1 puts the DMA transfer into cyclic mode. In cyclic mode the controller will re-start a transfer again once it has finished. In cyclic mode no end-of-transfer interrupts will be generated.
0x104 0x0410 DEST_ADDRESS AXI DMA Controller
[31:0] DEST_ADDRESS RW This register contains the destination address of the transfer. The address needs to be aligned to the bus width. This register is only valid if the DMA channel has been configured for write to memory support.
0x105 0x0414 SRC_ADDRESS AXI DMA Controller
[31:0] SRC_ADDRESS RW This register contains the source address of the transfer. The address needs to be aligned to the bus width. This register is only valid if the DMA channel has been configured for read from memory support.
0x106 0x0418 X_LENGTH AXI DMA Controller
[23:0] X_LENGTH RW Number of bytes to transfer - 1.
0x107 0x041c Y_LENGTH AXI DMA Controller
[23:0] Y_LENGTH RW Number of rows to transfer - 1. Note, this field is only valid if the DMA channel has been configured with 2D transfer support.
0x108 0x0420 DEST_STRIDE AXI DMA Controller
[23:0] DEST_STRIDE RW The number of bytes between the start of one row and the next row for the destination address. Needs to be aligned to the bus width. Note, this field is only valid if the DMA channel has been configured with 2D transfer support and write to memory support.
0x109 0x0424 SRC_STRIDE AXI DMA Controller
[23:0] SRC_STRIDE RW The number of bytes between the start of one row and the next row for the source address. Needs to be aligned to the bus width. Note, this field is only valid if the DMA channel has been configured with 2D transfer and read from memory support.
0x10a 0x0428 TRANSFER_DONE AXI DMA Controller
[X] TRANSFER_DONE RO If bit X is set in this register the transfer with ID X has been completed. The bit will automatically be cleared when a new transfer with this ID is queued and will be set when the transfer has been completed.
0x10b 0x042c ACTIVE_TRANSFER_ID AXI DMA Controller
[4:0] ACTIVE_TRANSFER_ID RO ID of the currently active transfer. When no transfer is active this register will be equal to the TRANSFER_ID register.
0x10c 0x0430 STATUS AXI DMA Controller
[31:0] RESERVED RO This register is reserved for future usage. Reading it will always return 0.
0x10d 0x0434 CURRENT_DEST_ADDRESS AXI DMA Controller
[31:0] CURRENT_DEST_ADDRESS RO Address to which the next data word is written to. This register is only valid if the DMA channel has been configured for write to memory support.
0x10e 0x0438 CURRENT_SRC_ADDRESS AXI DMA Controller
[31:0] CURRENT_SRC_ADDRESS RO Address form which the next data word is read. This register is only valid if the DMA channel has been configured for read from memory support.
Tue Aug 19 09:27:29 2014
/srv/wiki.analog.com/data/pages/resources/fpga/xilinx/hints/pcore_register_map.txt · Last modified: 13 Apr 2016 17:07 by andrei_g