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--- resources:fpga:xilinx:fmc:fmc-imageon [02 Jul 2012 19:05] – [Running Demo (SDK) Program] rejeesh kutty
+++ resources:fpga:xilinx:fmc:fmc-imageon [20 Dec 2023 12:02] (current) – Add obsolesce notice Stefan-Robert Raus
@@ Line 1: / Line 1: @@
-====== FMC-IMAGEON Xilinx ML605 Reference Design ======
+====== FMC-IMAGEON Xilinx Reference Design ======
+<note warning>**NOTE:**\\
+Support for the fmc-imageon is discontinued starting with 2022_r2 Kuiper Linux release and it will not be supported in future releases. Last Kuiper Linux release that contains pre-build files is 2021_r2. Check this [[:resources:tools-software:linux-software:adi-kuiper_images:release_notes|link]] to see all Kuiper releases.
+</note>
 ===== Introduction =====
-The [[http://www.em.avnet.com/en-us/design/drc/Pages/HDMI-Input-Output-FMC-module.aspx|FMC-IMAGEON]] is a HDMI input/output FMC card that provides high definition video interface for Xilinx FPGAs. The HDMI input interface is implemented with the [[adi>ADV7611|ADV7611]], a 165MHz, 24bit pixel output, HDCP capable HDMI 1.4a receiver. The HDMI output interface is implemented with the [[adi>ADV7511]], a 225MHz, 36bit deep color, HDMI 1.4 transmitter. This reference design provides the video and audio interface between the FPGA and ADV7511/ADV7611 on board. The video uses a 16bit 422 YCbCr interface and the audio uses a single bit SPDIF interface in both directions.
+The [[https://products.avnet.com/shop/en/ema/kits-and-tools/development-kits/aes-fmc-imageon-v2000c-g-3074457345623596557/|FMC-IMAGEON]] is a HDMI input/output FMC card that provides high definition video interface for Xilinx FPGAs. The HDMI input interface is implemented with the [[adi>ADV7611|ADV7611]], a 165MHz, 24bit pixel output, HDCP capable HDMI 1.4a receiver. The HDMI output interface is implemented with the [[adi>ADV7511]], a 225MHz, 36bit deep color, HDMI 1.4 transmitter. This reference design provides the video and audio interface between the FPGA and ADV7511/ADV7611 on board. The video uses a 16bit 422 YCbCr interface and the audio uses a single bit SPDIF interface in both directions.
+===== Supported Devices =====
+  * [[https://products.avnet.com/shop/en/ema/kits-and-tools/development-kits/aes-fmc-imageon-v2000c-g-3074457345623596557/|FMC-IMAGEON ]]
-**HW Platform(s):** [[http://www.xilinx.com/ml605|Virtex-6 ML605 (Xilinx)]] and [[http://www.em.avnet.com/en-us/design/drc/Pages/HDMI-Input-Output-FMC-module.aspx|FMC-IMAGEON (Avnet)]].\\
+===== Supported Carriers =====
-**System:** Microblaze, AXI, UART
-===== Quick Start Guide =====
+  * [[http://zedboard.org/product/zedboard|ZedBoard]]
-The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal, a HDMI display device and the programmer (IMPACT). You will need sdk/xmd to run the demo program.
 ==== Required Hardware ====
-  * ML605 and FMC-IMAGEON boards.
+  * One of the supported carrier and FMC-IMAGEON boards.
   * HDMI Monitor (should be capable of supporting 1080p and/or 720p for the demo files).
 ==== Required Software ====
-  * Xilinx ISE 14.1 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
+  * We upgrade the Xilinx tools on every release. The supported version number can be found in our [[https://github.com/analogdevicesinc/hdl/tree/master | git repository ]].
   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
-==== Bit file ====
-The default setup and contents allows three different demos on the board.
-|Test pattern (1080p)   |Use **sw/cf_adv7x11.bit**, this setup uses 1080p, image is an incrementing pattern and no audio. This bit file may be used for data integrity of video display (DMA and HDMI interfaces). The cable must be used to loopback for error free run.|
-|Test pattern (720p)    |Use **sw/cf_adv7x11_720p.bit**, this setup uses 720p, otherwise same as the previous one. It shows how to change the pixel clock without reprogramming the device or changing the hardware. The cable must be used to loopback for error free run.|
-|Demo Image (1080p)     |Use **sw/cf_adv7x11.bit** and **sw/cf_adv7x11_demo.elf**, this program sets the hardware for 1080p, displays the logo and generates a clicking sound for audio. You will need to use xmd or sdk to run this program (details below). |
-==== Running Demo (SDK) Program ====
-To begin make the following connections (see image below):
-  * Connect the IMAGEON card to the FMC HPC connector in ML605 (The design uses HPC, but card is FMC LPC compatible).
-  * Connect an HDMI cable between FMC-IMAGEON board HDMI out and the HDMI monitor. If you are running the bit files to verify the interfaces connect a cable from HDMI out to HDMI in (no monitor required).
-  * Connect two USB cables from the PC to the //JTAG// and //UART// USB connectors on ML605.
-  * Connect power to ML605 and the HDMI monitor.
-After the hardware setup, turn the power on to the ML605 and the HDMI monitor.
-{{.:cf_adv7x11_setup.jpg?200|Hardware setup}}
-The instructions here use xmd command line, running inside the sw directory. You can also use SDK GUI to program and run the elf files. Set the UART terminal to **57600** baud rate. If programming was successful, you should be seeing messages appear on the terminal as shown below. In all the three setups, press 'q' to exit the loop. After exiting the loop, the software sets the device to enable CSC. **The images will look different before and after CSC being enabled.** \\
-|Test Pattern (1080p) |Test Pattern (720p) |DEMO Image (1080p) |
-|Loopback Mode |Loopback Mode |Monitor Mode |
-|Program the device.    |Program the device.           |Program and run the elf file. |
-|fpga -f cf_adv7x11.bit |fpga -f cf_adv7x11_720p.bit   |fpga -f cf_adv7x11.bit  |
-|:::                    |:::                           |connect mb mdm  |
-|:::                    |:::                           |stop  |
-|:::                    |:::                           |dow cf_adv7x11_demo.elf  |
-|:::                    |:::                           |run  |
-|{{.:cf_adv7x11_uart.jpg?200|Terminal}} |{{.:cf_adv7x11_720p_uart.jpg?200|Terminal}} |{{.:cf_adv7x11_demo_uart.jpg?200|Terminal}} |
-|{{.:cf_adv7x11_monitor.jpg?200|Display}} |{{.:cf_adv7x11_720p_monitor.jpg?200|Display}} |{{.:cf_adv7x11_demo_monitor.jpg?200|Display}} |
-There should not be any errors reported by TPM. If you have not connected the loopback cable, the receive side will have errors.
 ===== Using the reference design =====
@@ Line 64: / Line 32: @@
 ==== Functional description ====
-|{{.:cf_adv7x11_bd.jpg?200|Block Diagram}} |
+=== Xilinx block diagram ===
+{{resources:fpga:xilinx:fmc:fmc-imageon:imageon_Xilinx.svg?800|HDL Block Diagram}}
-The reference design consists of two independent pcore modules.
+=== FMC-IMAGEON block diagram ===
+{{resources:fpga:xilinx:fmc:fmc-imageon:imageon_fmc_1.svg?600|HDL Block Diagram}}
-The video part consists of a Xilinx VDMA interface and the ADV7511/ADV7611 video interface. The video interface consists of a 16bit YCbCr 422 with embedded synchorinzation signals.
+The reference design consists of two independent IP modules.
-==== Video Transmit (VDMA to HDMI) ====
+The video part consists of an AXI DMAC interface and the ADV7511/ADV7611 video interface. The video interface consists of a 16bit YCbCr 422 with embedded synchronization signals.
-In the transmit direction, the VDMA streams frame data to this core. The internal buffers of this pcore are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The pixel clock is generated internal to the device and must be configured for the correct pixel frequency. It also allows a programmable color pattern for debug purposes. A zero to one transition on the enable bits trigger the corresponding action for HDMI enable and color pattern enable.
+==== Video Transmit (DMA to HDMI) ====
+In the transmit direction, the DMA streams frame data to this core. The internal buffers of this IP are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The pixel clock is generated internal to the device and must be configured for the correct pixel frequency. It also allows a programmable color pattern for debug purposes. A zero to one transition on the enable bits trigger the corresponding action for HDMI enable and color pattern enable.
 The reference design defaults to the 1080p video mode. Users may change the video settings by programming the video size registers. The core requires a corresponding pixel clock to generate the video. This clock must be generated externally.
@@ Line 82: / Line 54: @@
 A color pattern register provides a quick check of any RGB values on the monitor. If enabled, the register data is used as the pixel data for the entire frame.
-==== Video Receive (HDMI to VDMA) ====
+==== Video Receive (HDMI to DMA) ====
-In the receive direction, the HDMI data is first decoded and the synchronization signals are generated. The core then streams video data to VDMA. The internal buffers of this pcore are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The core runs at the pixel clock from ADV7611.
+In the receive direction, the HDMI data is first decoded and the synchronization signals are generated. The core then streams video data to DMA. The internal buffers of this IP are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The core runs at the pixel clock from ADV7611.
-The core decodes the active video size from the received data and compares it against an expected video size. If they do not match, the core will NOT stream data to VDMA to avoid possible lock up conditions in the VDMA core due to byte length mismatches. Also, the reference design performs color space conversion (YCbCr to RGB) and up sampling (422 to 444). If bypassed, the lower 16bits of DDR data is passed to the VDMA interface as it is.
+The core decodes the active video size from the received data and compares it against an expected video size. If they do not match, the core will NOT stream data to DMA to avoid possible lock up conditions in the DMA core due to byte length mismatches. Also, the reference design performs color space conversion (YCbCr to RGB) and up sampling (422 to 444). If bypassed, the lower 16bits of DDR data is passed to the DMA interface as it is.
 Test pattern generators and monitors are provided at each interface and clock domain boundaries. The default configuration is in loop back mode with the HDMI interface acting as a direct pass through.
@@ Line 92: / Line 64: @@
 ==== Audio ====
-The audio part consists of a Xilinx DMA interface and the ADV7511 spdif audio interface. The audio clock is derived from the bus clock. A programmable register (see below) controls the division factor. The audio data is read from the DDR as two 16bit words for the left and right channels. It is then transmitted on the SPDIF frame. The sample frequency and format may be controlled using the registers below. The reference design defaults to 48KHz.
+The audio part consists of an AXI DMAC interface and the ADV7511 spdif audio interface. The audio clock is derived from the bus clock. A programmable register (see below) controls the division factor. The audio data is read from the DDR as two 16bit words for the left and right channels. It is then transmitted on the SPDIF frame. The sample frequency and format may be controlled using the registers below. The reference design defaults to 48KHz.
 ==== Registers ====
-Please refer to the regmap.txt file inside the pcores.
+{{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}}
+{{page>:resources:fpga:docs:hdl:regmap## HDMI Transmit (axi_hdmi_tx)&nofooter&noeditbtn}}
+{{page>:resources:fpga:docs:hdl:regmap##HDMI Receive (axi_hdmi_rx) &nofooter&noeditbtn}}
 ==== Audio Registers (axi_spdif_tx) ====
@@ Line 111: / Line 87: @@
 |      | 0    | 0       | audio             | Data format is non-audio (0x1) or audio (0x0) (RO). |
 | 1. For AXI-Lite byte addresses, multiply by 4. |||||
-===== Downloads =====
+===== Using the ADV7511 Transmitter Library =====
-{{.:cf_adv7x11.tar.gz|ML605 Reference Design Source Code}}\\
+The transmitter library is a collection of APIs that provide a consistent interface to ADV7511.
+The library is a software layer that sits between the application and the TX hardware. The library is intended to serve two purposes:
+  * Provide the application with a set of APIs that can be used to configure HDMI TX hardware without the need for low-level register access. This makes the application portable across different revisions of the hardware and even across different hardware modules.
+  * Provide basic services to aid the application in controlling the TX module, such as interrupt service routine, HDCP high-level control and status information.
-===== Notes =====
+The Demo project uses the ADV7511 Transmitter Library.
+The project is an example of how to:
+  * Initialize the ADV7511 High-Definition Multimedia Interface (HDMI®) transmitter.
+  * Check current AVR operating mode and depending on this result set the AV mute state.
+  * Display an image and play a sound.
-The following Xilinx files are removed from the tar file as per licensing terms.
+The project contains 2 components: the Demo project files and the ADV7511 Transmitter Library. All the components have to be downloaded from the links provided in the **Downloads** section.
-  * axi_hdmi_16b_es_v1_00_a/hdl/vhdl/GenXlib_utils.vhd
+==== Software Setup ====
-  * axi_hdmi_16b_es_v1_00_a/hdl/vhdl/ImageXlib_utils.vhd
+The **ADV7511 Transmitter Library Demo** contains a folder called //**SDK_Workspace**// which stores the Xilinx SDK project files needed to build the no-OS software and also the .bit files with the HDL design that must be programmed into the FPGA.
-  * axi_hdmi_16b_es_v1_00_a/hdl/vhdl/GenXlib_arch.vhd
+These are the steps that need to be followed to recreate the software project:
-  * axi_hdmi_16b_es_v1_00_a/hdl/vhdl/ImageXlib_arch.vhd
+  * Copy the //**SDK_Workspace**// folder on your PC. Make sure that the path where it is stored does not contain any spaces.
-  * axi_hdmi_16b_es_v1_00_a/hdl/vhdl/convert444to422.vhd
+  * Copy the library file to the //**SDK_Workspace/sw/lib**// folder.
-  * axi_hdmi_16b_es_v1_00_a/hdl/vhdl/convert444to422_wrap.vhd
+{{:resources:fpga:xilinx:fmc:fmc-imageon:lib_files.png?600|Library file}}
-  * axi_hdmi_16b_es_v1_00_a/hdl/vhdl/convert422to444.vhd
+  * Copy the library headers to the //**SDK_Workspace/sw/inc**// folder.
-  * axi_hdmi_16b_es_v1_00_a/hdl/vhdl/convert422to444_wrap.vhd
+{{:resources:fpga:xilinx:fmc:fmc-imageon:inc_files.png?600|Library headers}}
-  * axi_hdmi_16b_es_v1_00_a/hdl/vhdl/color_space_pkg.vhd
+  * Copy the ADV7511 Transmitter Library Demo files to the //**SDK_Workspace/sw/src**// folder.
-  * axi_hdmi_16b_es_v1_00_a/hdl/vhdl/Xil_RGB2YCrCb.vhd
+{{:resources:fpga:xilinx:fmc:fmc-imageon:src_files.png?600|ADV7511 Transmitter Library Demo files}}
-  * axi_hdmi_16b_es_v1_00_a/hdl/vhdl/Xil_YCrCb2RGB.vhd
+  * Open the Xilinx SDK. When the SDK starts it asks for a to provide a folder where to store the workspace. Any folder can be provided.
-  * axi_hdmi_16b_es_v1_00_a/hdl/vhdl/csc_rgb_to_ycrcb422.vhd
+  * In the SDK select the //**File->Import**// menu option to import the software projects into the workspace.
-  * axi_hdmi_16b_es_v1_00_a/hdl/vhdl/csc_ycrcb422_to_rgb.vhd
+{{:resources:fpga:xilinx:fmc:fmc-imageon:file_import.png?300|Import Projects}}
+  * In the //Import// window select the //**General->Existing Projects into Workspace**// option.
-To use the reference design as it is, you must obtain these files from Xilinx.
+{{:resources:fpga:xilinx:fmc:fmc-imageon:existing_project_import.png?300|Existing Projects Import}}
+  * In the //Import Projects// window select the //**SDK_Workspace**// folder as root directory. After the root directory is chosen the projects that reside in that directory will appear in the //Projects// list. Press //Finish// to finalize the import process.
-===== Tar file contents =====
+{{:resources:fpga:xilinx:fmc:fmc-imageon:projects_import.png?300|Projects Import}}
+  * The //Project Explorer// window now shows the projects that exist in the workspace and the files for each project. The SDK should automatically build the projects and the //Console// window will display the result of the build. If the build is not done automatically select the //**Project->Build Automatically**// menu option.
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
+{{:resources:fpga:xilinx:fmc:fmc-imageon:project_explorer.png?300|Project Explorer}}
-| license.txt | ADI license & copyright information. |
-| system.mhs  | MHS file. |
-| system.xmp  | XMP file (use this file to build the reference design). |
-| data/       | UCF file and/or DDR MIG project files. |
-| docs/       | Documentation files (Please note that this wiki page is the documentation for the reference design). |
-| sw/         | Software (Xilinx SDK) & bit file(s). |
-| cf_lib/edk/pcores/     | Reference design core file(s) (Xilinx EDK). |
+===== Downloads =====
-===== More information =====
+**HDL Reference Designs:**
-  * [[ez>community/fpga|Ask questions about the FPGA reference design]]
+{{page>resources/fpga/docs/hdl/downloads_insert#fmcimageong}}
+**ADV7511 Transmitter Library Demo Software**
+<WRAP round download 80%>
+\\
+ * **ADV7511 Transmitter Library: ** https://www.analog.com/media/en/dsp-hardware-software/software-modules/ADV7511_API_Library.exe\\
+ * **ADV7511 Transmitter Library Demo files: ** https://github.com/analogdevicesinc/no-OS/tree/adv7511_rework/projects/adv7511\\
+</WRAP>
+{{page>resources/fpga/docs/hdl/downloads_insert#help_support}}

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