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This version (07 Nov 2012 14:53) was approved by Andrei Cozma.

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FMC-IMAGEON Xilinx ML605 Reference Design

Introduction

The FMC-IMAGEON is a HDMI input/output FMC card that provides high definition video interface for Xilinx FPGAs. The HDMI input interface is implemented with the ADV7611, a 165MHz, 24bit pixel output, HDCP capable HDMI 1.4a receiver. The HDMI output interface is implemented with the ADV7511, a 225MHz, 36bit deep color, HDMI 1.4 transmitter. This reference design provides the video and audio interface between the FPGA and ADV7511/ADV7611 on board. The video uses a 16bit 422 YCbCr interface and the audio uses a single bit SPDIF interface in both directions.

HW Platform(s): Virtex-6 ML605 (Xilinx) and FMC-IMAGEON (Avnet).
System: Microblaze, AXI, UART

Quick Start Guide

The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal, a HDMI display device and the programmer (IMPACT). You will need sdk/xmd to run the demo program.

Required Hardware

ML605 and FMC-IMAGEON boards.
HDMI Monitor (should be capable of supporting 1080p and/or 720p for the demo files).

Required Software

Xilinx ISE 14.1 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.

Bit file

The default setup and contents allows three different demos on the board.

Test pattern (1080p)	Use sw/cf_adv7x11.bit, this setup uses 1080p, image is an incrementing pattern and no audio. This bit file may be used for data integrity of video display (DMA and HDMI interfaces). The cable must be used to loopback for error free run.
Test pattern (720p)	Use sw/cf_adv7x11_720p.bit, this setup uses 720p, otherwise same as the previous one. It shows how to change the pixel clock without reprogramming the device or changing the hardware. The cable must be used to loopback for error free run.
Demo Image (1080p)	Use sw/cf_adv7x11.bit and sw/cf_adv7x11_demo.elf, this program sets the hardware for 1080p, displays the logo and generates a clicking sound for audio. You will need to use xmd or sdk to run this program (details below).

Running Demo (SDK) Program

To begin make the following connections (see image below):

Connect the IMAGEON card to the FMC HPC connector in ML605 (The design uses HPC, but card is FMC LPC compatible).
Connect an HDMI cable between FMC-IMAGEON board HDMI out and the HDMI monitor. If you are running the bit files to verify the interfaces connect a cable from HDMI out to HDMI in (no monitor required).
Connect two USB cables from the PC to the JTAG and UART USB connectors on ML605.
Connect power to ML605 and the HDMI monitor.

After the hardware setup, turn the power on to the ML605 and the HDMI monitor.

The instructions here use xmd command line, running inside the sw directory. You can also use SDK GUI to program and run the elf files. Set the UART terminal to 57600 baud rate. If programming was successful, you should be seeing messages appear on the terminal as shown below. In all the three setups, press 'q' to exit the loop. After exiting the loop, the software sets the device to enable CSC. The images will look different before and after CSC being enabled.

Test Pattern (1080p)	Test Pattern (720p)	DEMO Image (1080p)
Loopback Mode	Loopback Mode	Monitor Mode
Program the device.	Program the device.	Program and run the elf file.
fpga -f cf_adv7x11.bit	fpga -f cf_adv7x11_720p.bit	fpga -f cf_adv7x11.bit
		connect mb mdm
		stop
		dow cf_adv7x11_demo.elf
		run

There should not be any errors reported by TPM. If you have not connected the loopback cable, the receive side will have errors.

Using the reference design

Functional description

The reference design consists of two independent pcore modules.

The video part consists of a Xilinx VDMA interface and the ADV7511/ADV7611 video interface. The video interface consists of a 16bit YCbCr 422 with embedded synchorinzation signals.

Video Transmit (VDMA to HDMI)

In the transmit direction, the VDMA streams frame data to this core. The internal buffers of this pcore are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The pixel clock is generated internal to the device and must be configured for the correct pixel frequency. It also allows a programmable color pattern for debug purposes. A zero to one transition on the enable bits trigger the corresponding action for HDMI enable and color pattern enable.

The reference design defaults to the 1080p video mode. Users may change the video settings by programming the video size registers. The core requires a corresponding pixel clock to generate the video. This clock must be generated externally.

Note that the pixel frequency for 1080p is 148.5MHz.

The reference design reads 24bits of RGB data from DDR and performs color space conversion (RGB to YCbCr) and down sampling (444 to 422). If bypassed, the lower 16bits of DDR data is passed to the HDMI interface as it is.

A color pattern register provides a quick check of any RGB values on the monitor. If enabled, the register data is used as the pixel data for the entire frame.

Video Receive (HDMI to VDMA)

In the receive direction, the HDMI data is first decoded and the synchronization signals are generated. The core then streams video data to VDMA. The internal buffers of this pcore are small (1k) and do NOT buffer any frames as such. Additional resources may cause loss of synchronization due to DDR bandwidth requirements. The video core is capable of supporting any formats through a set of parameter registers (given below). The core runs at the pixel clock from ADV7611.

The core decodes the active video size from the received data and compares it against an expected video size. If they do not match, the core will NOT stream data to VDMA to avoid possible lock up conditions in the VDMA core due to byte length mismatches. Also, the reference design performs color space conversion (YCbCr to RGB) and up sampling (422 to 444). If bypassed, the lower 16bits of DDR data is passed to the VDMA interface as it is.

Test pattern generators and monitors are provided at each interface and clock domain boundaries. The default configuration is in loop back mode with the HDMI interface acting as a direct pass through.

Audio

The audio part consists of a Xilinx DMA interface and the ADV7511 spdif audio interface. The audio clock is derived from the bus clock. A programmable register (see below) controls the division factor. The audio data is read from the DDR as two 16bit words for the left and right channels. It is then transmitted on the SPDIF frame. The sample frequency and format may be controlled using the registers below. The reference design defaults to 48KHz.

Registers

Please refer to the regmap.txt file inside the pcores.

Audio Registers (axi_spdif_tx)

QW Address¹	Bits	Default	Name	Description
0x00	23:20	0	mode	Sample format 0 to 8 (0-16bit, 8-24bit).
	15:8	0	ratio	Clock divider for the transmit frequency = bus_clock/(1+ratio).
	1	0	txdata	Transmit data buffer enable (0x1) or disable (0x0).
	0	0	txenable	Transmitter enable (0x1) or disable (0x0).
0x01	7:6	0	frequency	Sample frequency 0(44.1KHz), 1(48KHz), 2(32KHz) or 3(sample rate converter) (RO).
	3	0	gstat	Generation status original/commercially pre-recorded data (0x1) or none (0x0) (RO).
	2	0	pre-emphasis	Pre-emphasis 50/15s (0x1) or none (0x0) (RO).
	1	0	copy	Copy permitted (0x1) or inhibited (0x0) (RO).
	0	0	audio	Data format is non-audio (0x1) or audio (0x0) (RO).
1. For AXI-Lite byte addresses, multiply by 4.

Downloads

ML605 Reference Design Source Code

Notes

The following Xilinx files are removed from the tar file as per licensing terms.

axi_hdmi_16b_es_v1_00_a/hdl/vhdl/GenXlib_utils.vhd
axi_hdmi_16b_es_v1_00_a/hdl/vhdl/ImageXlib_utils.vhd
axi_hdmi_16b_es_v1_00_a/hdl/vhdl/GenXlib_arch.vhd
axi_hdmi_16b_es_v1_00_a/hdl/vhdl/ImageXlib_arch.vhd
axi_hdmi_16b_es_v1_00_a/hdl/vhdl/convert444to422.vhd
axi_hdmi_16b_es_v1_00_a/hdl/vhdl/convert444to422_wrap.vhd
axi_hdmi_16b_es_v1_00_a/hdl/vhdl/convert422to444.vhd
axi_hdmi_16b_es_v1_00_a/hdl/vhdl/convert422to444_wrap.vhd
axi_hdmi_16b_es_v1_00_a/hdl/vhdl/color_space_pkg.vhd
axi_hdmi_16b_es_v1_00_a/hdl/vhdl/Xil_RGB2YCrCb.vhd
axi_hdmi_16b_es_v1_00_a/hdl/vhdl/Xil_YCrCb2RGB.vhd
axi_hdmi_16b_es_v1_00_a/hdl/vhdl/csc_rgb_to_ycrcb422.vhd
axi_hdmi_16b_es_v1_00_a/hdl/vhdl/csc_ycrcb422_to_rgb.vhd

To use the reference design as it is, you must obtain these files from Xilinx.

Tar file contents

The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.

license.txt	ADI license & copyright information.
system.mhs	MHS file.
system.xmp	XMP file (use this file to build the reference design).
data/	UCF file and/or DDR MIG project files.
docs/	Documentation files (Please note that this wiki page is the documentation for the reference design).
sw/	Software (Xilinx SDK) & bit file(s).
cf_lib/edk/pcores/	Reference design core file(s) (Xilinx EDK).

More information

Ask questions about the FPGA reference design

Wiki

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Table of Contents

FMC-IMAGEON Xilinx ML605 Reference Design

Introduction