// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
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// ***************************************************************************
// ***************************************************************************
// Rejeesh.Kutty@Analog.com (c) Analog Devices Inc.
// ***************************************************************************
// ***************************************************************************
// REGISTER MAP
// ***************************************************************************
// ***************************************************************************
// ---------------------------------------------------------------------------
// Address
// QW     Byte   Bits     Description
// ---------------------------------------------------------------------------
// 0x00   0x00   [31: 0]  version[31:0]         32'h00010061  (1.0a)
// ---------------------------------------------------------------------------
// 0x01   0x04   [ 1: 1]  sw_reset              SW Reset
//               [ 0: 0]  start                 Start
// ---------------------------------------------------------------------------
// 0x02   0x08   [15: 0]  clk_out_1             Clock Out Register 1
// 0x03   0x0c   [15: 0]  clk_out_2             Clock Out Register 2
// 0x04   0x10   [15: 0]  clk_div               Clock Divide Register
// 0x05   0x14   [15: 0]  clk_fb_1              Clock Feedback Register 1
// 0x06   0x18   [15: 0]  clk_fb_1              Clock Feedback Register 2
// 0x07   0x1c   [15: 0]  lock_1                Lock Register 1
// 0x08   0x20   [15: 0]  lock_2                Lock Register 2
// 0x09   0x24   [15: 0]  lock_3                Lock Register 3
// 0x0a   0x28   [15: 0]  filter_1              Filter Register 1
// 0x0b   0x2c   [15: 0]  filter_2              Filter Register 2
//
// The above registers map into the corresponding MMCM registers and/or ports
// ---------------------------------------------------------------------------
// 0x1f   0x7c   [ 1: 1]  mmcm_rst              MMCM reset (0x1) state (RO)
//               [ 0: 0]  mmcm_locked           MMCM locked (0x1) state (RO)
//
// ---------------------------------------------------------------------------
// ***************************************************************************
// ***************************************************************************
