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resources:fpga:xilinx:fmc:ad9739a [22 Jul 2019 13:59] – Update no-OS driver link Andrei Drimbareanresources:fpga:xilinx:fmc:ad9739a [12 Feb 2021 11:55] (current) – [Quick Start Guide] -update video tutorial link Dan Nechita
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 The reference design has been tested on ML605(Virtex-6), KC705(Kintex-7), VC707(Virtex-7) and ZC706 (Zynq) boards. The notes below refer to ML605, however the procedure is same for the other boards. Currently, we fully support only the ZC706 Vivado based design. Please make sure that you have downloaded and are using the correct design files for your board. All you need is the hardware and a PC running a UART terminal.  The reference design has been tested on ML605(Virtex-6), KC705(Kintex-7), VC707(Virtex-7) and ZC706 (Zynq) boards. The notes below refer to ML605, however the procedure is same for the other boards. Currently, we fully support only the ZC706 Vivado based design. Please make sure that you have downloaded and are using the correct design files for your board. All you need is the hardware and a PC running a UART terminal. 
  
-{{analogTV>1423927819001}}+A video tutorial is available: {{analogTV>1423927819001}}
 ==== Required Hardware ==== ==== Required Hardware ====
   * ML605/KC705/VC707/AC701 board (use the corresponding design file).   * ML605/KC705/VC707/AC701 board (use the corresponding design file).
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   * Xilinx ISE Design Suite 14.4   * Xilinx ISE Design Suite 14.4
   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
-  * [[http://wiki.analog.com/resources/eval/dpg/dacsoftwaresuite | DAC Software Suite (optional)]]+  * [[/resources/eval/dpg/dacsoftwaresuite | DAC Software Suite (optional)]]
  
 ==== Running Demo (SDK) Program ==== ==== Running Demo (SDK) Program ====
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 The reference design consists of two functional modules, a DDS/LVDS interface and a SPI interface. It is part of an AXI based microblaze system as shown in the block diagram below. It is designed to support linux running on microblaze. All other peripherals are available from Xilinx as IP cores. The reference design consists of two functional modules, a DDS/LVDS interface and a SPI interface. It is part of an AXI based microblaze system as shown in the block diagram below. It is designed to support linux running on microblaze. All other peripherals are available from Xilinx as IP cores.
  
-{{:resources:fpga:xilinx:fmc:ad9739a_ebz:cf_ad9739a_bd.jpg?400|block diagram}}+=== Xilinx block diagram === 
 +{{:resources:fpga:xilinx:fmc:ad9739a_ebz:ad9739a_fmc_xilinx.svg?500|Xilinx HDL Block Diagram}}
  
 +=== AD9739A FMC Card block diagram ===
 +{{:resources:fpga:xilinx:fmc:ad9739a_ebz:ad9739a_fmc_card_1.svg?400|Xilinx HDL Block Diagram}}
  
 The DDS consists of a Xilinx DDS IP core and a DDR based data generator. The core generates 6 samples at every fDAC/3 clock cycles for each port of AD9739A. The DDS consists of a Xilinx DDS IP core and a DDR based data generator. The core generates 6 samples at every fDAC/3 clock cycles for each port of AD9739A.
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 <WRAP round help 80%> <WRAP round help 80%>
 \\ \\
-  * Questions? [[https://ez.analog.com/community/fpga|Ask Help & Support]].+  * Questions? [[ez>community/fpga|Ask Help & Support]].
 \\ \\
 </WRAP> </WRAP>
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 <WRAP round help 80%> <WRAP round help 80%>
  
-  * [[http://www.analog.com/en/digital-to-analog-converters/high-speed-da-converters/ad9739a/products/product.html|Purchase AD9739A-FMC-EBZ]]+  * [[adi>en/digital-to-analog-converters/high-speed-da-converters/ad9739a/products/product.html|Purchase AD9739A-FMC-EBZ]]
   * [[http://www.vita.com/fmc|VITA's FMC info]]   * [[http://www.vita.com/fmc|VITA's FMC info]]
   * [[ez>community/fpga|Ask questions about the FPGA reference design]]   * [[ez>community/fpga|Ask questions about the FPGA reference design]]
   * [[ez>community/data_converters/high-speed_dacs|Ask questions about the AD9739A]]   * [[ez>community/data_converters/high-speed_dacs|Ask questions about the AD9739A]]
 </WRAP> </WRAP>
resources/fpga/xilinx/fmc/ad9739a.1563796779.txt.gz · Last modified: 22 Jul 2019 13:59 by Andrei Drimbarean

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