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resources:fpga:xilinx:fmc:ad9434 [09 Jan 2021 00:39] – user interwiki links Robin Getzresources:fpga:xilinx:fmc:ad9434 [30 Oct 2023 17:47] (current) – [AD9434-FMC] Added a port for ZEDBOARD and updated the whole page. Cristian Mihai Popa
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 ====== AD9434 Native FMC Card ====== ====== AD9434 Native FMC Card ======
    
-===== Introduction =====+===== Overview =====
  
-The [[adi>AD9434]] is a 12-bit monolithic sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. This reference design includes a data capture interface and the external DDR-DRAM interface for sample storage. It allows programming the device and monitoring it's internal status registers. The board also provides other options to drive the clock and analog inputs of the ADC.+The [[adi>AD9434]] is a 12-bit monolithic sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use.  
 +The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems.  
 +All necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution.  
 +This reference design includes a data capture interface and the external DDR-DRAM interface for sample storage. It allows programming the device and  
 +monitoring its internal status registers. The board also provides other options to drive the clock and analog inputs of the ADC.
  
 ===== Supported Devices ===== ===== Supported Devices =====
  
   * [[adi>en/analog-to-digital-converters/ad-converters/ad9434/products/EVAL-AD9434/eb.html| AD9434-FMC-500EBZ]]   * [[adi>en/analog-to-digital-converters/ad-converters/ad9434/products/EVAL-AD9434/eb.html| AD9434-FMC-500EBZ]]
-  
-===== Functional Description ====== 
- 
-The reference design is built on a Zynq based system parameterized for linux. It consists of three functional modules, a LVDS interface, a PN monitor and a DMA interface. The LVDS interface captures and buffers data from the ADC. The data is captured using ISERDES primitives and is captured 4 samples wide at 1/4th of the ADC clock (125MHz at 500MHz ADC clock). The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software. 
-By default, the board is configured to use the onboard clock. 
- 
  
 ===== Supported Carriers ===== ===== Supported Carriers =====
  
   * [[xilinx>ZC706]] LPC Slot   * [[xilinx>ZC706]] LPC Slot
-  * [[xilinx>ML605]] Legacy+  * [[https://digilent.com/reference/programmable-logic/zedboard/start|ZEDBOARD]] LPC Slot
  
-===== Downloads =====+===== Block Design ====== 
 + 
 +==== Block diagram ==== 
 + 
 +{{ :resources:fpga:xilinx:fmc:ad9434_fmc.svg? 600 | Block Diagram }} 
 + 
 +==== Clock scheme ==== 
 + 
 +An external clock source can be connected to J201, but this need to be done by configuring P100. See schematic for more info. See **Board files** section below. 
 + 
 +==== CPU/Memory interconnects ==== 
 + 
 +The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL. Check-out the tables below: 
 + 
 +CPU: 
 + 
 +<WRAP round 80%> 
 +|< 100% 20% 18% 12% 25% 25%>| 
 +^Instance ^Zynq address ^ 
 +| axi_ad9434 | 0x44A0_0000 | 
 +| axi_ad9434_dma| 0x44A3_0000 | 
 +</WRAP> 
 + 
 +==== SPI connections ==== 
 + 
 +<WRAP round 80%> 
 +|< 100% 20% 18% 12% 25% 25%>| 
 +^SPI Type ^SPI manager instance ^SPI subordinate ^CSB ^ 
 +| PS | SPI 0 | AD9517     | 1 | 
 +| PS | SPI 0 | AD9434BCPZ | 0 | 
 +</WRAP> 
 + 
 +==== Interrupts ==== 
 + 
 +Below are the Programmable Logic interrupts used in this project. 
 + 
 +<WRAP round 80%> 
 +|< 100% 20% 18% 12% 25% 25%>| 
 +^Instance name ^HDL ^Linux Zynq ^Actual Zynq ^ 
 +| axi_ad9783_dma | 13 | 57 | 89 | 
 +</WRAP> 
 + 
 +===== Building the HDL projects ====== 
 + 
 +The design is built upon ADI's generic HDL reference design framework. ADI does not distribute the bit/elf files of these projects so they must be built from the sources available  
 +[[https://github.com/analogdevicesinc/hdl|here]]. To get the source you must clone the HDL repository, and then build the project as follows. 
 + 
 +On Linux/Cygwin/WSL: 
 +<code> 
 +user@analog:~$ cd hdl/projects/ad9434_fmc/zc706 
 +user@analog:~/hdl/projects/ad9434_fmc/zc706$ make 
 +</code> 
 + 
 +A more comprehensive build guide can be found in the [[https://github.com/analogdevicesinc/hdl/blob/master/docs/user_guide/build_hdl.rst|build_hdl]] user guide. 
 + 
 +===== AD9434_FMC Board files =====
  
 Board Files: Board Files:
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 </WRAP> </WRAP>
  
-{{page>resources/fpga/docs/hdl/downloads_insert#ad9434fmc}} +==== Setup guide =====
- +
-{{page>resources/fpga/docs/hdl/downloads_insert#help_support}} +
- +
-===== ML605 Xilinx Reference Design (Obsolete) ===== +
- +
-==== Quick Start Guide ==== +
- +
-The reference design has been tested with ML605. It should be easily portable to other boards such as KC705 and VC707, only the ISERDES primitive, UCF and MHS files need to be changed. The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal and the programmer (IMPACT). This bit file configuration also captures the test mode outputs of ADC.+
  
 ==== Required Hardware ==== ==== Required Hardware ====
  
-  * ML605 board+  * ZC706/ZEDBOARD
   * AD9434-FMC board (the default setup uses onboard clock)   * AD9434-FMC board (the default setup uses onboard clock)
 +  * SD card (at least 16gb)
   * Signal generator (for data)   * Signal generator (for data)
 +  * 1x SMA cable to connect the signal generator to the ad9434_fmc
 +  * 1x Ethernet cable 
  
 ==== Required Software ==== ==== Required Software ====
  
-  * Xilinx ISE (Programmer (IMPACT) is sufficient for the demo and is available on Webpack). Use the latest version or the one used in the reference design. +  * A UART terminal (Tera Term/Hyperterminal), Baud rate 115200. 
-  * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600. +  * IIO Oscilloscope to capture data
-  * Xilinx Chipscope Analyzer (for signal capture plot).+
  
-==== Running Demo (SDK) Program ====+==== Hardware configuration ====
  
-To begin, connect the AD9434-FMC board to the FMC-LPC connector of ML605 board (see image below). Connect power and two USB cables from the PC to the //JTAG// and //UART// USB connectors on the edge of the ML605. **The demo program uses the default board configuration that uses an on-board clock.** Connect a signal source to the AIN SMA (J100) connector of the FMC card. After the hardware setup, turn the power on to the ML605. +For the ZC706 to boot from the SD card, the SW11 switch should be configured like this: **0110**, from left to right(see [[https://docs.xilinx.com/v/u/en-US/ug954-zc706-eval-board-xc7z045-ap-soc|ZC706 user guide]], Device Configuration section).  
-  +The VADJ required: 2.5V.
-{{:resources:fpga:xilinx:fmc:cf_ad9434_setup.jpg?200|Hardware setup}}+
  
-Start IMPACT, and initialize the JTAG chain. The program should recognize the Virtex 6 device. Start a UART terminal (set to 57600 baud rate) and then program the device. If programming was successful, you should be seeing messages appear on the terminal as shown in the figure below. After reading some default registers in the AD9434 and AD9517, the program enables different test patterns available on the ADC.+For ZEDBOARD place the VADJ Jumper on 2.5V. 
  
-{{:resources:fpga:xilinx:fmc:cf_ad9434_uart.jpg?200|Terminal}}+The ad9434_fmc should be configured this way:
  
-After patterns and prbs sequences are verified, if no errors are present, you may use the chipscope busplot to see the captured signal (see below). The ADC data is available 4-samples wide at 125MHz. The most recent sample is at the most significant bits of the captured data.+This is and example of configuration for the AD9434-FMC-500EBZ board. In this configuration we don't need an external source of signal generator for the CLKIN  
 +port, because it will be configured to use the internal oscillator.
  
-{{:resources:fpga:xilinx:fmc:cf_ad9434_busplot.jpg?200|Chipscope Busplot}}+  * Jumper P100: on pins 1 and 2 (this Jumper configures the source of clock; as it this now, it uses the internal signal generator) 
 +  * Jumper J300: on row pins 3 and 4, or PD and AGND(see jumper schematic next to it on the board) 
 +  * Jumper P400: on pins 5 and 6 
 +  * Jumper P300: no configuration
  
-==== Using the Reference Design ====+==== First time running ==== 
 + 
 +To begin, connect the AD9434-FMC board to the FMC-LPC connector of ZC706. Connect the power source for ZC706,  
 +the Ethernet cable and the USB cable for UART communication. Program the SD card with the latest image of Analog Devices  
 +Kuiper Linux. Then, from projects folder, copy the **BOOT.BIN** file and the **devicetree.dtb** file in the /root folder.  
 +Also, from the **zynq-common** folder copy the uImage file in the /root folder. Insert the SD card in the card  
 +slot of the ZC706 and start the FPGA. Using a program for UART communication, you will be able to see the FPGA  
 +booting up the Kuiper system. After the boot, you will be able to find the ip address and other files of the system. Below, is a photo of the setup. 
 +  
 +{{:resources:fpga:xilinx:fmc:ad9434_zc706_setup.png?500| Setup }} 
 + 
 +After finding the IP address, open IIO Oscilloscope and choose manual connection. Write **ip:your_ip_address** and click on refresh or press enter. In the textboxes below should appear different information and 
 +you should see the name of the carrier and the name of the FMC. After connecting to the ZC706, you may proceed with the testing of the board. Click on **File->New plot** to get a new plot. As mentioned,  
 +you need a external signal generator. If you generate a signal with a 10MHz frequency and 100mVpp amplitude, you should get something like this: 
 + 
 +{{:resources:fpga:xilinx:fmc:ad9434_zc706_10mhz_1000samples.png?600| IIO Oscilloscope capture }}
  
 ==== Functional Description ==== ==== Functional Description ====
  
-The reference design is built on a microblaze based system parameterized for linux. It consists of three functional modules, a LVDS interface, a PN monitor and a DMA interface. The LVDS interface captures and buffers data from the ADC. The data is captured using ISERDES primitives and is captured 4 samples wide at 1/4th of the ADC clock (125MHz at 500MHz ADC clock). The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.+The reference design is built on a microblaze based system parameterized for Linux. It consists of three functional modules, a LVDS interface, a PN monitor and a DMA interface. The LVDS interface captures and buffers data from the ADC. The data is captured using ISERDES primitives and is captured 4 samples wide at 1/4th of the ADC clock (125MHz at 500MHz ADC clock). The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
  
 ==== Registers ==== ==== Registers ====
  
-Refer to the regmap.txt file inside the pcores directory.+Refer to the regmap.txt file inside the pcores directory or from [[https://github.com/analogdevicesinc/hdl/tree/master/docs/regmap|here]].
  
 ==== Clock Selection ==== ==== Clock Selection ====
  
-The board provides different (some modification maybe necessary) possible clock path for clocking the AD9434. +The board provides different possible clock path for clocking the AD9434(some modification may be necessary).
  
-==== Downloads ==== +===== Resources =====
-FPGA Referece Designs: +
-<WRAP round download 80%> +
- +
-  * **ML605 (Source files):** {{:resources:fpga:xilinx:fmc:cf_ad9434_ml605_edk_14_4_2013_03_29.tar.gz}} +
-  * **ML605 (Bit/SW files):** {{:resources:fpga:xilinx:fmc:cf_ad9434_ml605_sw_14_4_2013_03_29.tar.gz}}+
  
 +Hardware related:
 +<WRAP 80%>
 +  * [[adi>EVAL-AD9434]]
 +  * [[adi>AD9434]]
 </WRAP> </WRAP>
  
-Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.+HDL related:
  
-==== Tar File Contents ====+[[https://github.com/analogdevicesinc/hdl/tree/f81532d1d792d9104e3d2290155c0155893e3d7f/projects/ad9434_fmc|AD9434_fmc HDL project]]
  
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.+<WRAP 80%> 
 +|< 100% 20% 18% 12% 25% 25%>| 
 +^IP name ^Source code link ^Documentation link ^ 
 +| axi_ad9434 | [[https://github.com/analogdevicesinc/hdl/tree/f81532d1d792d9104e3d2290155c0155893e3d7f/library/axi_ad9434|axi_ad9434 HDL]] | - | 
 +| axi_dmac | [[https://github.com/analogdevicesinc/hdl/tree/f81532d1d792d9104e3d2290155c0155893e3d7f/library/axi_dmac|axi_dmac HDL]] | [[https://wiki.analog.com/resources/fpga/docs/axi_dmac|axi_dmac doc]] | 
 +| axi_clkgen | [[https://github.com/analogdevicesinc/hdl/tree/f81532d1d792d9104e3d2290155c0155893e3d7f/library/axi_clkgen|axi_clkgen HDL]] | [[https://wiki.analog.com/resources/fpga/docs/axi_clkgen|axi_clkgen doc]] | 
 +| axi_hdmi_tx | [[https://github.com/analogdevicesinc/hdl/tree/f81532d1d792d9104e3d2290155c0155893e3d7f/library/axi_hdmi_tx|axi_hdmi_tx HDL]] | [[https://wiki.analog.com/resources/fpga/docs/axi_hdmi_tx|axi_hdmi_tx doc]] | 
 +| axi_spdif_tx | [[https://github.com/analogdevicesinc/hdl/tree/f81532d1d792d9104e3d2290155c0155893e3d7f/library/axi_spdif_tx|axi_spdif_tx HDL]] | - | 
 +| axi_sysid | [[https://github.com/analogdevicesinc/hdl/tree/f81532d1d792d9104e3d2290155c0155893e3d7f/library/axi_sysid|axi_sysid HDL]] | [[https://wiki.analog.com/resources/fpga/docs/axi_sysid|System ID doc]] | 
 +| sysid_rom | [[https://github.com/analogdevicesinc/hdl/tree/f81532d1d792d9104e3d2290155c0155893e3d7f/library/sysid_rom|sysid_rom HDL]] | [[https://wiki.analog.com/resources/fpga/docs/axi_sysid|System ID doc]] | 
 +</WRAP>
  
-| license.txt | ADI license & copyright information. | +Software related: 
-| system.mhs | MHS file. | +<WRAP 80%> 
-| system.xmp | XMP file (use this file to build the reference design). | +  * [[https://github.com/analogdevicesinc/linux/blob/master/arch/arm/boot/dts/zynq-zc706-adv7511-ad9434-fmc-500ebz.dts|Linux device tree]] 
-| data/   | UCF file and/or DDR MIG project files. | +  * [[https://github.com/analogdevicesinc/linux/blob/9197af5e6cfe0f804df581581348cbb81e5f0190/drivers/iio/adc/ad9467.c#L143|AD9434 driver]] 
-| docs/   | Documentation files (Please note that this wiki page is the documentation for the reference design). | +</WRAP>
-| sw/     | Software (Xilinx SDK) & bit file(s). | +
-| ../cf_lib/edk/pcores/* | The pcores directory. |+
  
resources/fpga/xilinx/fmc/ad9434.txt · Last modified: 30 Oct 2023 17:47 by Cristian Mihai Popa

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