The AD9434 is a 12-bit monolithic sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. This reference design includes a data capture interface and the external DDR-DRAM interface for sample storage. It allows programming the device and monitoring its internal status registers. The board also provides other options to drive the clock and analog inputs of the ADC.
An external clock source can be connected to J201, but this need to be done by configuring P100. See schematic for more info. See Board files section below.
The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL. Check-out the tables below:
CPU:
Instance | Zynq address |
---|---|
axi_ad9434 | 0x44A0_0000 |
axi_ad9434_dma | 0x44A3_0000 |
SPI Type | SPI manager instance | SPI subordinate | CSB |
---|---|---|---|
PS | SPI 0 | AD9517 | 1 |
PS | SPI 0 | AD9434BCPZ | 0 |
Below are the Programmable Logic interrupts used in this project.
Instance name | HDL | Linux Zynq | Actual Zynq |
---|---|---|---|
axi_ad9783_dma | 13 | 57 | 89 |
The design is built upon ADI's generic HDL reference design framework. ADI does not distribute the bit/elf files of these projects so they must be built from the sources available here. To get the source you must clone the HDL repository, and then build the project as follows.
On Linux/Cygwin/WSL:
user@analog:~$ cd hdl/projects/ad9434_fmc/zc706 user@analog:~/hdl/projects/ad9434_fmc/zc706$ make
A more comprehensive build guide can be found in the build_hdl user guide.
For the ZC706 to boot from the SD card, the SW11 switch should be configured like this: 0110, from left to right(see ZC706 user guide, Device Configuration section). The VADJ required: 2.5V.
For ZEDBOARD place the VADJ Jumper on 2.5V.
The ad9434_fmc should be configured this way:
This is and example of configuration for the AD9434-FMC-500EBZ board. In this configuration we don't need an external source of signal generator for the CLKIN port, because it will be configured to use the internal oscillator.
To begin, connect the AD9434-FMC board to the FMC-LPC connector of ZC706. Connect the power source for ZC706, the Ethernet cable and the USB cable for UART communication. Program the SD card with the latest image of Analog Devices Kuiper Linux. Then, from projects folder, copy the BOOT.BIN file and the devicetree.dtb file in the /root folder. Also, from the zynq-common folder copy the uImage file in the /root folder. Insert the SD card in the card slot of the ZC706 and start the FPGA. Using a program for UART communication, you will be able to see the FPGA booting up the Kuiper system. After the boot, you will be able to find the ip address and other files of the system. Below, is a photo of the setup.
After finding the IP address, open IIO Oscilloscope and choose manual connection. Write ip:your_ip_address and click on refresh or press enter. In the textboxes below should appear different information and you should see the name of the carrier and the name of the FMC. After connecting to the ZC706, you may proceed with the testing of the board. Click on File→New plot to get a new plot. As mentioned, you need a external signal generator. If you generate a signal with a 10MHz frequency and 100mVpp amplitude, you should get something like this:
The reference design is built on a microblaze based system parameterized for Linux. It consists of three functional modules, a LVDS interface, a PN monitor and a DMA interface. The LVDS interface captures and buffers data from the ADC. The data is captured using ISERDES primitives and is captured 4 samples wide at 1/4th of the ADC clock (125MHz at 500MHz ADC clock). The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
Refer to the regmap.txt file inside the pcores directory or from here.
The board provides different possible clock path for clocking the AD9434(some modification may be necessary).
Hardware related:
HDL related:
IP name | Source code link | Documentation link |
---|---|---|
axi_ad9434 | axi_ad9434 HDL | - |
axi_dmac | axi_dmac HDL | axi_dmac doc |
axi_clkgen | axi_clkgen HDL | axi_clkgen doc |
axi_hdmi_tx | axi_hdmi_tx HDL | axi_hdmi_tx doc |
axi_spdif_tx | axi_spdif_tx HDL | - |
axi_sysid | axi_sysid HDL | System ID doc |
sysid_rom | sysid_rom HDL | System ID doc |
Software related: