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| resources:fpga:peripherals:jesd204 [03 Jun 2019 15:52] – [Linux] Michael Hennerich | resources:fpga:peripherals:jesd204 [25 Mar 2024 08:30] (current) – Update license link Paul Pop |
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| ====== JESD204 Interface Framework ====== | ====== JESD204 Interface Framework ====== |
| |
| The JESD204, JESD204A and the JESD204B data converter serial interface standard was created through the JEDEC committee to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs (field-programmable gate arrays). Fewer interconnects simplifies layout and allows smaller form factor realization without impacting overall system performance. These attributes are important to address the system size and cost constraints of a range of high speed ADC applications, including wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA) transceiver architectures, software-defined radios, portable instrumentation, medical ultrasound equipment, and Mil/Aero applications such as radar and secure communications. Analog Devices is an original participating member of the JEDEC JESD204 standards committee and we have concurrently developed compliant data converter technology and tools, and a comprehensive product roadmap to fully enable our customers to take advantage of this significant interfacing breakthrough. | The JESD204, JESD204A, JESD204B and the JESD204C data converter serial interface standard was created through the JEDEC committee to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs (field-programmable gate arrays). Fewer interconnects simplifies layout and allows smaller form factor realization without impacting overall system performance. These attributes are important to address the system size and cost constraints of a range of high speed ADC applications, including wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA) transceiver architectures, software-defined radios, portable instrumentation, medical ultrasound equipment, and Mil/Aero applications such as radar and secure communications. Analog Devices is an original participating member of the JEDEC JESD204 standards committee and we have concurrently developed compliant data converter technology and tools, and a comprehensive product roadmap to fully enable our customers to take advantage of this significant interfacing breakthrough. |
| |
| Analog Devices supplies a full-stack supporting JESD204B which provides a fully integrated system level experience. This solution includes | Analog Devices supplies a full-stack supporting JESD204B/C which provides a fully integrated system level experience. This solution includes |
| <WRAP round download 65%> | <WRAP round download 65%> |
| * [[#jesd204b_rapid_prototyping_platforms|Reference hardware platforms]] for rapid-prototyping | * [[#jesd204b_rapid_prototyping_platforms|Reference hardware platforms]] for rapid-prototyping |
| * [[#fpga_hdl_support|FPGA HDL]] for interfacing JESD204B ADCs, DACs, and RF Transceivers | * [[#fpga_hdl_support|FPGA HDL]] for interfacing JESD204B/C ADCs, DACs, and RF Transceivers |
| * [[#software_support|Software]] to configure the converter devices and FPGA HDL peripherals | * [[#software_support|Software]] to configure the converter devices and FPGA HDL peripherals |
| </WRAP> | </WRAP> |
| ===== How to Obtain a License ===== | ===== How to Obtain a License ===== |
| |
| When customers and partners download software from github, or e-mail downloaded software to someone, they are obligated to comply to the terms and conditions of the [[https://github.com/analogdevicesinc/hdl/blob/dev/library/jesd204/README.md|Software License Agreement]]. The core is released under two difference licenses. You may choose either: | When customers and partners download software from github, or e-mail downloaded software to someone, they are obligated to comply to the terms and conditions of the [[https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIJESD204|Software License Agreement]]. The core is released under two difference licenses. You may choose either: |
| * Commercial licenses may be purchased from Analog Devices, Inc. or any authorized distributor by ordering [[adi>AD-IP-JESD204]]. This will allow you to use the core in a closed system. | * Commercial licenses may be purchased from Analog Devices, Inc. or any authorized distributor by ordering [[adi>en/design-center/evaluation-hardware-and-software/jesd204-interface-framework.html|IP-JESD204]]. This will allow you to use the core in a closed system. |
| * GPL 2, this allows you to use the core for any purpose, but you must release anything else that links to the JESD204 core (this would normally be your algorithmic IP). You do not need to sign anything purchase anything to use the JESD204 core under the GPL license. | * GPL 2, this allows you to use the core for any purpose, but you must release anything else that links to the JESD204 core (this would normally be your algorithmic IP). You do not need to sign anything purchase anything to use the JESD204 core under the GPL license. |
| |
| There is only one core, the only difference is the license and support. If you have a question about the license: you can email [[jesd204-licensing@analog.com]]. | There is only one core, the only difference is the license and support. If you have a question about the license: you can email [[jesd204-licensing@analog.com]]. |
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| |
| ===== FPGA HDL Support ===== | ===== FPGA HDL Support ===== |
| {{ :resources:fpga:peripherals:jesd204_layers2.png?100|}} | {{ :resources:fpga:peripherals:jesd204_layers2.png?100|}} |
| |
| The JESD204B standard defines multiple layers, each layer being responsible for a particular function. The Analog Devices JESD204B HDL solution follows the standard here and defines 4 layers. Physical layer, link layer, transport layer and application layer. For the first three layers Analog Devices provides standard components that can be linked up to provide a full JESD204B protocol processing chain. | The JESD204B/C standard defines multiple layers, each layer being responsible for a particular function. The Analog Devices JESD204B/C HDL solution follows the standard here and defines 4 layers. Physical layer, link layer, transport layer and application layer. For the first three layers Analog Devices provides standard components that can be linked up to provide a full JESD204B/C protocol processing chain. |
| |
| Depending on the FPGA and converter combinations that are being interfaced different components can be chosen for the physical and transport layer. The FPGA defines which physical layer component should be used and the interfaced converter defines which transport layer component should be used. | Depending on the FPGA and converter combinations that are being interfaced different components can be chosen for the physical and transport layer. The FPGA defines which physical layer component should be used and the interfaced converter defines which transport layer component should be used. |
| |
| The link layer component is selected based on the direction of the JESD204B link. | The link layer component is selected based on the direction of the JESD204B/C link. |
| |
| The application layer is user defined and can be used to implement application specific signal processing. | The application layer is user defined and can be used to implement application specific signal processing. |
| |
| Physical layer peripherals are responsible for interfacing and configuring the high-speed serial transceivers. | Physical layer peripherals are responsible for interfacing and configuring the high-speed serial transceivers. |
| | Currently we have support for GTXE2, GTHE3, GTHE4, GTYE4 for Xilinx and Arria 10 transceivers for Intel. |
| |
| * [[..:docs:axi_adxcvr|AXI_ADXCVR]]: JESD204B Gigabit Transceiver Register Configuration Peripheral | * [[..:docs:axi_adxcvr|AXI_ADXCVR]]: JESD204B Gigabit Transceiver Register Configuration Peripheral |
| ==== Link Layer ==== | ==== Link Layer ==== |
| |
| Link layer peripherals are responsible for JESD204B protocol handling, including scrambling/descrambling, lane alignment, character replacement and alignment monitoring. | Link layer peripherals are responsible for JESD204B/C protocol handling, including scrambling/descrambling, lane alignment, character replacement and alignment monitoring. |
| |
| * [[.:jesd204:axi_jesd204_tx|JESD204B Transmit Peripheral]]: JESD204B Link Layer Transmit Peripheral | * [[.:jesd204:axi_jesd204_tx|JESD204B/C Transmit Peripheral]]: JESD204B/C Link Layer Transmit Peripheral |
| * [[.:jesd204:axi_jesd204_rx|JESD204B Receive Peripheral]]: JESD204B Link Layer Receive Peripheral | * [[.:jesd204:axi_jesd204_rx|JESD204B/C Receive Peripheral]]: JESD204B/C Link Layer Receive Peripheral |
| |
| ==== Transport Layer ==== | ==== Transport Layer ==== |
| Transport layer peripherals are responsible for converter specific data framing and de-framing. | Transport layer peripherals are responsible for converter specific data framing and de-framing. |
| |
| * [[resources:fpga:peripherals:jesd204:jesd204_tpl_adc|ADC JESD204B Transport Peripheral]] : JESD204B Transport Layer Receive Peripheral | * [[resources:fpga:peripherals:jesd204:jesd204_tpl_adc|ADC JESD204B/C Transport Peripheral]] : JESD204B/C Transport Layer Receive Peripheral |
| * [[resources:fpga:peripherals:jesd204:jesd204_tpl_dac|DAC JESD204B Transport Peripheral]] : JESD204B Transport Layer Transmit Peripheral | * [[resources:fpga:peripherals:jesd204:jesd204_tpl_dac|DAC JESD204B/C Transport Peripheral]] : JESD204B/C Transport Layer Transmit Peripheral |
| | |
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| ==== Interfaces ==== | ==== Interfaces ==== |
| |
| Interfaces are a well-defined collection of wires that are used to communicate between components. The following interfaces are used to connect components of the HDL JESD204B processing stack. | Interfaces are a well-defined collection of wires that are used to communicate between components. The following interfaces are used to connect components of the HDL JESD204B/C processing stack. |
| ===== Software Support ===== | ===== Software Support ===== |
| |
| ==== Linux ==== | ==== Linux ==== |
| |
| * [[resources:tools-software:linux-drivers:jesd204:axi_jesd204_tx|JESD204B Transmit Linux Driver]]: Linux driver for the JESD204B transmit core. | * [[resources:tools-software:linux-drivers:jesd204:jesd204-fsm-framework|JESD204 (FSM) Interface Linux Kernel Framework]] |
| * [[resources:tools-software:linux-drivers:jesd204:axi_jesd204_rx|JESD204B Receive Linux Driver]]: Linux driver for the JESD204B receive core. | * [[resources:tools-software:linux-drivers:jesd204:axi_jesd204_tx|JESD204B/C Transmit Linux Driver]]: Linux driver for the JESD204B transmit core. |
| | * [[resources:tools-software:linux-drivers:jesd204:axi_jesd204_rx|JESD204B/C Receive Linux Driver]]: Linux driver for the JESD204B receive core. |
| | * [[resources:tools-software:linux-drivers:jesd204:axi_adxcvr|JESD204B/C AXI_ADXCVR Highspeed Transceivers Linux Driver]] |
| * [[resources:tools-software:linux-software:jesd_eye_scan|JESD204B Statistical Eyescan Application]] | * [[resources:tools-software:linux-software:jesd_eye_scan|JESD204B Statistical Eyescan Application]] |
| * [[resources:tools-software:linux-software:jesd_status|JESD204B Status Utility]] | * [[resources:tools-software:linux-software:jesd_status|JESD204B Status Utility]] |
| * [[resources:tools-software:linux-drivers:iio-dds:axi-dac-dds-hdl|AXI DAC HDL Linux Driver]] | * [[resources:tools-software:linux-drivers:iio-dds:axi-dac-dds-hdl|AXI DAC HDL Linux Driver]] |
| * [[resources:tools-software:linux-drivers:iio-dds:ad9172|AD9172 DAC Linux Driver]] | * [[resources:tools-software:linux-drivers:iio-dds:ad9172|AD9172 DAC Linux Driver]] |
| | * [[resources:tools-software:linux-drivers:iio-mxfe:ad9081|AD9081 MxFE Linux Driver]] |
| | * [[resources:tools-software:linux-drivers:iio-transceiver:adrv9009|ADRV9009, ADRV9008 highly integrated, wideband RF transceiver Linux device driver]] |
| | * [[resources:tools-software:linux-drivers:iio-transceiver:ad9371|AD9371, AD9375 highly integrated, wideband RF transceiver Linux device driver]] |
| * [[resources:tools-software:linux-drivers:iio-adc:axi-adc-hdl|AXI ADC HDL Linux Driver]] | * [[resources:tools-software:linux-drivers:iio-adc:axi-adc-hdl|AXI ADC HDL Linux Driver]] |
| * [[resources:tools-software:linux-drivers:iio-adc:ad9208|AD9208 ADC Linux Driver]] | * [[resources:tools-software:linux-drivers:iio-adc:ad9208|AD9208 ADC Linux Driver]] |
| | * [[resources:tools-software:linux-drivers:iio-mxfe:ad9081|AD9081 MxFE Linux Driver]] |
| | * [[resources:tools-software:linux-drivers:iio-transceiver:adrv9009|ADRV9009, ADRV9008 highly integrated, wideband RF transceiver Linux device driver]] |
| | * [[resources:tools-software:linux-drivers:iio-transceiver:ad9371|AD9371, AD9375 highly integrated, wideband RF transceiver Linux device driver]] |
| |
| ==== No-OS ==== | ==== No-OS ==== |
| | * [[resources:tools-software:uc-drivers:jesd204:axi_adxcvr|ADI JESD204B/C AXI_ADXCVR Highspeed Transceivers No-OS Driver]] |
| | * [[resources:tools-software:uc-drivers:jesd204:axi_jesd204_rx|ADI JESD204B/C Receive Peripheral No-OS Driver]] |
| | * [[resources:tools-software:uc-drivers:jesd204:axi_jesd204_tx|ADI JESD204B/C Transmit Peripheral No-OS Driver]] |
| | * [[resources:tools-software:uc-drivers:jesd204:axi_adc_core|AXI ADC No-OS Driver]] |
| | * [[resources:tools-software:uc-drivers:jesd204:axi_dac_core|AXI DAC No-OS Driver]] |
| |
| ===== Tutorial ===== | ===== Tutorial ===== |
| - [[.:jesd204:tutorial:introduction|Introduction]] | - [[.:jesd204:tutorial:introduction|Introduction]] |
| - [[.:jesd204:tutorial:system_architecture|System Architecture]] | - [[.:jesd204:tutorial:system_architecture|System Architecture]] |
| - [[resources:fpga:docs:hdl:generic_jesd_bds|Generic JESD204B block designs]] | - [[resources:fpga:docs:hdl:generic_jesd_bds|Generic JESD204B block designs]]. This will help you understand the generic blocks for the next steps. |
| - [[.:jesd204:tutorial:hdl_xilinx|HDL Xilinx]] | - Checkout the [[resources:fpga:docs:build|HDL Source]], and then build either one of: |
| - [[.:jesd204:tutorial:hdl_altera|HDL Altera]] | - [[.:jesd204:tutorial:hdl_xilinx|HDL Xilinx]] |
| | - [[.:jesd204:tutorial:hdl_altera|HDL Altera]] |
| - [[.:jesd204:tutorial:linux|Linux]] | - [[.:jesd204:tutorial:linux|Linux]] |
| |
| ===== Example Projects ===== | ===== Example Projects ===== |
| |
| * [[:resources:fpga:xilinx:fmc:ad-fmcadc2-ebz|AD-FMCADC2-EBZ HDL Reference Design]] | * [[:resources:fpga:xilinx:fmc:ad-fmcadc2-ebz|AD-FMCADC2-EBZ Reference Design]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/fmcadc2/vc707|Xilinx VC707]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcadc2/vc707|Xilinx VC707]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/fmcadc2/zc706|Xilinx ZC706]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcadc2/zc706|Xilinx ZC706]] |
| * [[:resources:fpga:xilinx:fmc:ad-fmcadc3-ebz|AD-FMCADC3-EBZ HDL Reference Design]] | * [[:resources:fpga:xilinx:fmc:ad-fmcadc3-ebz|AD-FMCADC3-EBZ Reference Design]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/fmcadc2/vc707|Xilinx VC707]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcadc2/vc707|Xilinx VC707]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/fmcadc2/zc706|Xilinx ZC706]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcadc2/zc706|Xilinx ZC706]] |
| * [[:resources:fpga:xilinx:fmc:ad-fmcadc4-ebz|AD-FMCADC4-EBZ HDL Reference Design]] | * [[:resources:fpga:xilinx:fmc:ad-fmcadc4-ebz|AD-FMCADC4-EBZ Reference Design (retired)]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/fmcadc4/zc706| Xilinx ZC706]] | * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2018_r2/projects/fmcadc4/zc706| Xilinx ZC706]] |
| * [[:resources:fpga:xilinx:fmc:ad-fmcjesdadc1-ebz|AD-FMCJESDADC1-EBZ HDL Reference Design]] | * [[:resources:fpga:xilinx:fmc:ad-fmcjesdadc1-ebz|AD-FMCJESDADC1-EBZ Reference Design]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/fmcjesdadc1/a10gx| Intel A10GX]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcjesdadc1/kc705| Xilinx KC705]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/fmcjesdadc1/a10soc| Intel A10SOC]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcjesdadc1/vc707| Xilinx VC707]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/fmcjesdadc1/kc705| Xilinx KC705]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcjesdadc1/zc706| Xilinx ZC706]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/fmcjesdadc1/vc707| Xilinx VC707]] | * [[:resources:eval:user-guides:ad-fmcomms11-ebz|AD-FMCOMMS11-EBZ Reference Design]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/fmcjesdadc1/zc706| Xilinx ZC706]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/fmcomms11/zc706| Xilinx ZC706]] |
| * [[:resources:eval:user-guides:ad-fmcdaq2-ebz:reference_hdl|AD-FMCDAQ2-EBZ HDL Reference Design]] | * [[:resources:eval:user-guides:ad-fmcdaq2-ebz|AD-FMCDAQ2-EBZ Reference Design]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/daq2/a10gx | Intel A10GX]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/a10soc | Intel A10SOC]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/daq2/a10soc | Intel A10SOC]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/kc705 | Xilinx KC705]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/daq2/kc705 | Xilinx KC705]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/kcu105 | Xilinx KCU105]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/daq2/kcu105 | Xilinx KCU105]] | * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2018_r2/projects/daq2/vc707 | Xilinx VC707]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/daq2/vc707 | Xilinx VC707]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/zc706 | Xilinx ZC706]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/daq2/zc706 | Xilinx ZC706]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/zcu102 | Xilinx ZCU102]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/daq2/zcu102 | Xilinx ZCU102]] | * [[:resources:eval:user-guides:ad-fmcdaq3-ebz|AD-FMCDAQ3-EBZ Reference Design]] |
| * [[:resources:eval:user-guides:mykonos:reference_hdl|ADRV9371 HDL Reference Design]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq3/kcu105 | Xilinx KCU105]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/adrv9371x/a10gx| Intel A10GX]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq3/vcu118| Xilinx VCU118]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/adrv9371x/a10soc| Intel A10SOC]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq3/zc706 | Xilinx ZC706]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/adrv9371x/kcu105| Xilinx KCU105]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/daq3/zcu102 | Xilinx ZCU102]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/adrv9371x/zc706| Xilinx ZC706]] | * [[:resources:eval:user-guides:mykonos|ADRV9371 Reference Design]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1/projects/adrv9371x/zcu102| Xilinx ZCU102]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/adrv9371x/a10soc| Intel A10SOC]] |
| * [[:resources:eval:user-guides:adrv9009:reference_hdl|ADRV9009 HDL Reference Design]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/adrv9371x/kcu105| Xilinx KCU105]] |
| * [[https://github.com/analogdevicesinc/hdl/tree/hdl_2018_r1/projects/adrv9009/zcu102| Xilinx ZCU102]] | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/adrv9371x/zc706| Xilinx ZC706]] |
| | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/adrv9371x/zcu102| Xilinx ZCU102]] |
| | * [[:resources:eval:user-guides:adrv9009|ADRV9009 Reference Design]] |
| | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/adrv9009/zcu102| Xilinx ZCU102]] |
| | * [[:resources:eval:user-guides:adrv9009-zu11eg|ADRV9009-ZU11EG-SOM Reference Design]] |
| | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/adrv9009zu11eg| ADRV9009-ZU11EG-SOM]] |
| | * [[:resources:eval:user-guides:ad-dac-fmc-ebz|AD917X Reference Design]] |
| | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/dac_fmc_ebz/a10soc| Intel A10SOC]] |
| | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/dac_fmc_ebz/zc706| Xilinx ZC706]] |
| | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/dac_fmc_ebz/zcu102| Xilinx ZCU102]] |
| | * [[:resources:eval:user-guides:ad9081_fmca_ebz:ad9081_fmca_ebz_hdl| AD9081 Reference Design]] |
| | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/ad9081_fmca_ebz/zcu102| Xilinx ZCU102]] |
| | * [[https://github.com/analogdevicesinc/hdl/tree/master/projects/ad9081_fmca_ebz/vcu118| Xilinx VCU118]] |
| ===== Additional Information ===== | ===== Additional Information ===== |
| |
| ==== Technical Articles ==== | ==== Technical Articles ==== |
| |
| * [[http://www.analog.com/media/en/technical-documentation/technical-articles/JESD204B-Survival-Guide.pdf|JESD204B Survival Guide]] | * [[adi>media/en/technical-documentation/technical-articles/JESD204B-Survival-Guide.pdf|JESD204B Survival Guide]] |
| * [[http://www.analog.com/media/en/technical-documentation/technical-articles/Synchronizing-Sample-Clocks-of-a-Data-Converter-Array-Web.pdf|Synchronizing Sample Clocks of a Data Converter Array]] | * [[adi>media/en/technical-documentation/technical-articles/Synchronizing-Sample-Clocks-of-a-Data-Converter-Array-Web.pdf|Synchronizing Sample Clocks of a Data Converter Array]] |
| ==== JESD204B Rapid Prototyping Platforms ==== | ==== JESD204B Rapid Prototyping Platforms ==== |
| |
| * [[adi>EVAL-ADRV9371|ADRV9371]] ([[:resources:eval:user-guides:mykonos|User Guide]]) | * [[adi>EVAL-ADRV9371|EVAL-ADRV9371]] ([[:resources:eval:user-guides:mykonos|User Guide]]) |
| * [[adi>EVAL-ADRV9008-9009|ADRV9009]] ([[:resources:eval:user-guides:adrv9009|User Guide]]) | * [[adi>EVAL-ADRV9008-9009|EVAL-ADRV9008-9009]] ([[:resources:eval:user-guides:adrv9009|User Guide]]) |
| | * ADRV9009-ZU11EG ([[:resources:eval:user-guides:adrv9009-zu11eg|User Guide]]) |
| * [[adi>AD-FMCJESDADC1-EBZ|AD-FMCJESDADC1-EBZ]] | * [[adi>AD-FMCJESDADC1-EBZ|AD-FMCJESDADC1-EBZ]] |
| | * [[adi>AD-FMCOMMS11-EBZ|AD-FMCOMMS11-EBZ]] ([[:resources:eval:user-guides:ad-fmcomms11-ebz|User Guide]]) |
| * [[adi>AD-FMCADC2-EBZ|AD-FMCADC2-EBZ]] | * [[adi>AD-FMCADC2-EBZ|AD-FMCADC2-EBZ]] |
| * [[adi>EVAL-AD-FMCADC3-EBZ|AD-FMCADC3-EBZ]] | * [[adi>EVAL-AD-FMCADC3-EBZ|AD-FMCADC3-EBZ]] |
| * [[adi>EVAL-AD-FMCADC4-EBZ|AD-FMCADC4-EBZ]] | * [[adi>EVAL-AD-FMCADC4-EBZ|AD-FMCADC4-EBZ]](retired) |
| * [[adi>AD-FMCDAQ2-EBZ|AD-FMCDAQ2-EBZ]] ([[:resources:eval:user-guides:ad-fmcdaq2-ebz|User Guide]]) | * [[adi>AD-FMCDAQ2-EBZ|AD-FMCDAQ2-EBZ]] ([[:resources:eval:user-guides:ad-fmcdaq2-ebz|User Guide]]) |
| | * [[adi>EVAL-FMCDAQ3-EBZ|EVAL-FMCDAQ3-EBZ]] ([[:resources:eval:user-guides:ad-fmcdaq3-ebz|User Guide]]) |
| | * [[adi>EVAL-AD917X|EVAL-AD917X]] |
| |
| ==== JESD204B Analog-to-Digital Converters ==== | ==== JESD204B Analog-to-Digital Converters ==== |
| * [[adi>AD9691]]: 14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter | * [[adi>AD9691]]: 14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter |
| * [[adi>AD9694]]: 14-Bit, 500 MSPS JESD204B, Quad Analog-to-Digital Converter | * [[adi>AD9694]]: 14-Bit, 500 MSPS JESD204B, Quad Analog-to-Digital Converter |
| | * [[adi>AD9083]]: 16-Channel, 125 MHz Bandwidth, JESD204B Analog-to-Digital Converter |
| |
| ==== JESD204B Digital-to-Analog Converters ==== | ==== JESD204B Digital-to-Analog Converters ==== |
| * [[adi>ADRV9008-2]]: SDR Integrated, Dual RF Transmitter with Observation Path | * [[adi>ADRV9008-2]]: SDR Integrated, Dual RF Transmitter with Observation Path |
| |
| | ==== JESD204B/C Mixed-Signal Front Ends ==== |
| | * [[adi>AD9081]]: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and Quad, 12-Bit, 4GSPS RFADC |
| | * [[adi>AD9082]]: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and DUAL, 12-Bit, 6GSPS RFADC |
| ==== JESD204B Clocking Solutions ==== | ==== JESD204B Clocking Solutions ==== |
| |
| * [[adi>HMC7043]]: High Performance, 3.2 GHz, 14-Output Fanout Buffer | * [[adi>HMC7043]]: High Performance, 3.2 GHz, 14-Output Fanout Buffer |
| * [[adi>HMC7044]]: High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B | * [[adi>HMC7044]]: High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B |
| | * [[adi>LTC6952]]: Ultralow Jitter, 4.5GHz PLL, JESD204B/JESD204C |
| | |
