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resources:fpga:peripherals:jesd204:validation:testbenches [21 Jul 2021 14:50] – [System level testbenches] Laszlo Nagy | resources:fpga:peripherals:jesd204:validation:testbenches [22 Jul 2021 16:36] (current) – [Testbench architecture] Laszlo Nagy | ||
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The system level testbenches reside in a separate github repository: [[repo> | The system level testbenches reside in a separate github repository: [[repo> | ||
- | ==== Supported simulators: ==== | + | ==== Supported simulators ==== |
The test environment is built around Xilinx AXI VIPs so the only supported simulator is: | The test environment is built around Xilinx AXI VIPs so the only supported simulator is: | ||
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- | | + | |
==== List of JESD system level testbenches ==== | ==== List of JESD system level testbenches ==== | ||
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[[repo> | [[repo> | ||
+ | |||
+ | ==== Testbench architecture ==== | ||
+ | |||
+ | The devices under test (jesd204 components) are placed in a test harness which is made of several Xilinx verification IP's: clock and reset generators, AXI verification IPs to emulate the control side of the processor or to emulate a DDR storage module. | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | === SV API packages === | ||
+ | |||
+ | * [[https:// | ||
+ | * [[https:// | ||
+ | |||
+ | ==== How to run the tb ==== | ||
+ | |||
+ | Details on running the testbench you can find in the [[https:// | ||
+ | |||
+ | ===== Technical Support ===== | ||
+ | |||
+ | Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Clock, etc) via the [[ez> | ||
+ | encounter. | ||
+ | |||
+ | ===== More Information ===== | ||
+ | |||
+ | * [[: | ||