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This version (22 Jul 2021 16:36) was approved by Laszlo Nagy.

Table of Contents

JESD204 Testbenches

Various levels of testbenches are available from component level to system level covering the whole stack including physical layer, link layer and transport layer components.

Component level testbenches

Location of testbenches

The component level testbnenches are located in the hdl repository, near to the JESD204 IPs itself in the tb folder.

Component level testbenches

Supported simulators

The simulator can be selected through the SIMULATOR environment variable. Supported values are:

$SIMULATORSimulator name
modelsim Menthor/Siemens ModelSim/QuestaSim
xsim Xilinx Vivado
xcelium Cadence Xcelium
(default)Icarus Verilog (iverilog)

How to run the tb:

  1. open up a Cygwin or bash terminal
  2. go to the library/jesd204/tb folder
  3. set up the selected simulator by setting the $SIMULATOR environment variable with the corresponding value listed above.
  4. launch the simulation by executing one of the below scripts
    1. axi_jesd204_rx_regmap_tb
    2. axi_jesd204_tx_regmap_tb
    3. crc12_tb
    4. frame_align_tb
    5. jesd204_frame_align_replace_tb
    6. jesd204_frame_mark_tb
    7. loopback_64b_tb
    8. loopback_tb
    9. rx_cgs_tb
    10. rx_ctrl_tb
    11. rx_lane_tb
    12. rx_tb
    13. scrambler_64b_tb
    14. scrambler_tb
    15. soft_pcs_8b10b_sequence_tb
    16. soft_pcs_8b10b_table_tb
    17. soft_pcs_loopback_tb
    18. soft_pcs_pattern_align_tb
    19. tx_64b_tb
    20. tx_ctrl_phase_tb
    21. tx_tb

System level testbenches

The system level testbenches reside in a separate github repository: testbenches repo

Supported simulators

The test environment is built around Xilinx AXI VIPs so the only supported simulator is: 

- Xilinx Vivado matching the current hdl release version requirements

List of JESD system level testbenches

jesd_loopback - A generic testbench covering the ADI JESD framework physical layer, link layer and transport layer components, supporting 204B or 204C 64b66b operation modes.

jesd_loopback_64b - A JESD testbench with Xilinx PHY supporting only the 64b66b mode

Testbench architecture

The devices under test (jesd204 components) are placed in a test harness which is made of several Xilinx verification IP's: clock and reset generators, AXI verification IPs to emulate the control side of the processor or to emulate a DDR storage module.

SV API packages

  • adi_jesd204_pkg.sv - JESD204 link layer package, a collection of tasks and functions to high level control the link layer transmit and receive peripherals
  • adi_xcvr_pkg.sv - JESD204 physical layer package, a collection of tasks and functions to high level control and automatically configure the transceivers for a given lane rate and reference clock

How to run the tb

Details on running the testbench you can find in the README.md of each testbench and in the general README.md of the repository.

Technical Support

Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Clock, etc) via the EngineerZone under the GPL license. If you would like deterministic support when using this core with an ADI component, please investigate a commercial license. Using a non-ADI JESD204 device with this core is possible under the GPL, but Analog Devices will not help with issues you may encounter.

More Information

resources/fpga/peripherals/jesd204/validation/testbenches.txt · Last modified: 22 Jul 2021 16:36 by Laszlo Nagy

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