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resources:fpga:peripherals:jesd204:validation:testbenches [21 Jul 2021 14:39] – [List of JESD system level testbenches] Laszlo Nagyresources:fpga:peripherals:jesd204:validation:testbenches [22 Jul 2021 16:36] (current) – [Testbench architecture] Laszlo Nagy
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 ===== System level testbenches ===== ===== System level testbenches =====
  
-The system level testbenches reside in a separate github repository: [[repo>testbenches/tree/main | System level testbenches repo]]+The system level testbenches reside in a separate github repository: [[repo>testbenches/tree/main | testbenches ]] repo
  
-==== Supported simulators: ====+==== Supported simulators ==== 
 + 
 +The test environment is built around Xilinx AXI VIPs so the only supported simulator is:
      
-  * Xilinx Vivado (xsim)+  - Xilinx Vivado matching the current hdl release version requirements
  
 ==== List of JESD system level testbenches ==== ==== List of JESD system level testbenches ====
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 [[repo>testbenches/tree/main/jesd_loopback | jesd_loopback]] - A generic testbench covering the ADI JESD framework  physical layer, link layer and transport layer components, supporting 204B or 204C 64b66b operation modes. [[repo>testbenches/tree/main/jesd_loopback | jesd_loopback]] - A generic testbench covering the ADI JESD framework  physical layer, link layer and transport layer components, supporting 204B or 204C 64b66b operation modes.
  
-[[repo>testbenches/tree/main/jesd_loopback_64 | jesd_loopback_64]] - A JESD testbench with Xilinx PHY supporting 64b66b mode+[[repo>testbenches/tree/main/jesd_loopback_64b | jesd_loopback_64b]] - A JESD testbench with Xilinx PHY supporting only the 64b66b mode 
 + 
 +==== Testbench architecture ==== 
 + 
 +The devices under test (jesd204 components) are placed in a test harness which is made of several Xilinx verification IP's: clock and reset generators, AXI verification IPs to emulate the control side of the processor or to emulate a DDR storage module.  
 + 
 +{{ :resources:fpga:peripherals:jesd204:validation:examplesystemleveltestbench.jpg?nolink |}} 
 + 
 +=== SV API packages === 
 + 
 +  * [[https://www.github.com/analogdevicesinc/testbenches/blob/main/common/sv/adi_jesd204_pkg.sv | adi_jesd204_pkg.sv ]]  - JESD204 link layer package, a collection of tasks and functions to high level control the link layer transmit and receive peripherals 
 +  * [[https://www.github.com/analogdevicesinc/testbenches/blob/main/common/sv/adi_xcvr_pkg.sv | adi_xcvr_pkg.sv ]]  - JESD204 physical layer package, a collection of tasks and functions to high level control and automatically configure the transceivers for a given lane rate and reference clock  
 + 
 +==== How to run the tb ==== 
 + 
 +Details on running the testbench you can find in the [[https://github.com/analogdevicesinc/testbenches/blob/main/jesd_loopback/README.md | README.md]] of each testbench and in the general [[https://github.com/analogdevicesinc/testbenches/blob/main/README.md | README.md]] of the repository. 
 + 
 +===== Technical Support ===== 
 + 
 +Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Clock, etc) via the [[ez>community/fpga|EngineerZone]] under the GPL license. If you would like deterministic support when using this core with an ADI component, please investigate a commercial license. Using a non-ADI JESD204 device with this core is possible under the GPL, but Analog Devices will not help with issues you may 
 +encounter. 
 + 
 +===== More Information ===== 
 + 
 +  * [[:resources:fpga:peripherals:jesd204 | JESD204 High-Speed Serial Interface Support]]
  
  
resources/fpga/peripherals/jesd204/validation/testbenches.1626871172.txt.gz · Last modified: 21 Jul 2021 14:39 by Laszlo Nagy

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