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--- resources:fpga:peripherals:jesd204:jesd204_tpl_adc [06 May 2021 10:23] – [Interfaces and Signals] Laszlo Nagy
+++ resources:fpga:peripherals:jesd204:jesd204_tpl_adc [27 May 2021 16:03] – [Interfaces and Signals] Laszlo Nagy
@@ Line 110: / Line 110: @@
 Once the sync signal is received the data will start to flow and the ''ADC_SYNC'' status bit will reflect that with a deassertion.
+While the synchronization mechanism is armed, the ''adc_rst'' output signal is set so downstream logic can be cleared in order to have a fresh start once the trigger is received.
 ===== Software Support =====

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