Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revision | Last revisionBoth sides next revision | ||
| resources:fpga:peripherals:jesd204:axi_jesd204_rx [25 Aug 2022 17:55] – [64b/66b Link latency reduction] Laszlo Nagy | resources:fpga:peripherals:jesd204:axi_jesd204_rx [31 Aug 2022 11:18] – [64b/66b Link latency reduction] Laszlo Nagy | ||
|---|---|---|---|
| Line 469: | Line 469: | ||
| Once the slowest lane delay is identified, before enabling the links, SW needs to set the register '' | Once the slowest lane delay is identified, before enabling the links, SW needs to set the register '' | ||
| - | < | + | < |
| Where: | Where: | ||
resources/fpga/peripherals/jesd204/axi_jesd204_rx.txt · Last modified: 23 Jan 2024 10:40 by Adrian Costina