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resources:fpga:peripherals:jesd204:axi_jesd204_rx [08 Jun 2022 15:51] – [Signal and Interface Pins] Laszlo Nagyresources:fpga:peripherals:jesd204:axi_jesd204_rx [25 Aug 2022 17:55] – [64b/66b Link latency reduction] Laszlo Nagy
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 In this context the link clock will be lane rate/40 or lane rate/80 for 204B depending on DATA_PATH_WIDTH and lane rate / 66 for 204C 64B/66B,  however the device clock could vary based in the F parameter.  In this context the link clock will be lane rate/40 or lane rate/80 for 204B depending on DATA_PATH_WIDTH and lane rate / 66 for 204C 64B/66B,  however the device clock could vary based in the F parameter. 
 +
 +===== 64b/66b Link latency reduction  =====
 +Deterministic latency can be reduced by adjusting the release point of the elastic buffer in RX link layer. 
 +By default the release point of the elastic buffer is at the edge of LEMC.  
 +In case of 64b66b link the ''LATENCY'' register will indicate how many octets will the elastic buffer store before the default release point for that specific lane. The release point can be adjusted to bring it closer to the last arrival lane (that will have the least octets in the buffer) so minimizing the buffer usage and the latency in turn.  The ''LATENCY'' must be measured over multiple power-ups and bring-up sequence. Identify the slowest arrival lane (min value of the register). If multiple parallel links must be synchronized all lanes from all links must be included in the process. 
 +
 +Once the slowest lane delay is identified, before enabling the links, SW needs to set the register ''BUFFER_DEALY'' (0x240) from all parallel Rx links if exists based on the following formula: 
 +
 + <m>Buffer Delay = (F*K - min(latency regs + 32)) / TPLDW + 4</m>
 +
 +Where:
 +  * Buffer Delay - register 0x240 of the core
 +  * F*K - is the size of a multiframe in octets
 +  * ‘latency regs’ - is the measured latency of each lane observed during consecutive link bring-ups measured for all Rx links, see regs (0x304 + n*0x20)  where n = 0..L-1 ; L is number of lanes
 +  * TPLDW - TPL datapath width in octets. Can be read from the ''SYNTH_DATA_PATH_WIDTH'' (0x14) reg ''TPL_DATA_PATH_WIDTH'' field.
 +  
 +** This value it the absolute minimum. It is recommended to increase it slightly to have a better margin against power-up to power-up latency variations.**
 +
  
 ===== Software Support ===== ===== Software Support =====
resources/fpga/peripherals/jesd204/axi_jesd204_rx.txt · Last modified: 23 Jan 2024 10:40 by Adrian Costina

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