Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revision | Next revisionBoth sides next revision |
| resources:fpga:peripherals:jesd204:axi_jesd204_rx [14 Jan 2021 05:38] – use ez> interwiki links Robin Getz | resources:fpga:peripherals:jesd204:axi_jesd204_rx [25 Jan 2021 07:03] – [Interfaces and Signals] Laszlo Nagy |
|---|
| === Register Map Configuration Interface === | === Register Map Configuration Interface === |
| |
| The register map configuration interface can be accessed through the [[AXI4-Lite]] ''S_AXI'' interface. The interface is synchronous to the ''s_axi_aclk''. The ''s_axi_aresetn'' signal is used to reset the peripheral and should be asserted during system startup until the ''s_axi_aclk'' is active and stable. De-assertion of the reset signal should be synchronous to ''s_axi_aclk''. | The register map configuration interface can be accessed through the AXI4-Lite ''S_AXI'' interface. The interface is synchronous to the ''s_axi_aclk''. The ''s_axi_aresetn'' signal is used to reset the peripheral and should be asserted during system startup until the ''s_axi_aclk'' is active and stable. De-assertion of the reset signal should be synchronous to ''s_axi_aclk''. |
| |
| === JESD204 Control Signals === | === JESD204 Control Signals === |
| === User Data Interface (RX_DATA) === | === User Data Interface (RX_DATA) === |
| |
| User data is provided on the [[AXI4-Stream]] ''RX_DATA'' interface. The interface is a reduced AXI4-Stream interface and only features the TVALID flow control signal, but not the TREADY flow control signal. The behavior of the interface is as if the TREADY signal was always asserted. This means as soon as ''rx_valid'' is asserted a continuous stream of user data must be accepted from ''rx_data''. | User data is provided on the AXI4-Stream ''RX_DATA'' interface. The interface is a reduced AXI4-Stream interface and only features the TVALID flow control signal, but not the TREADY flow control signal. The behavior of the interface is as if the TREADY signal was always asserted. This means as soon as ''rx_valid'' is asserted a continuous stream of user data must be accepted from ''rx_data''. |
| |
| {{ :resources:fpga:peripherals:jesd204:jesd204_rx_rx_data_timing.png |}} | {{ :resources:fpga:peripherals:jesd204:jesd204_rx_rx_data_timing.png |}} |
