Wiki

Analog Devices Wiki

English
English
简体中文
简体中文
日本語
日本語
Руccкий
Руccкий

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revisionBoth sides next revision
resources:fpga:peripherals:jesd204:axi_jesd204_rx [18 Feb 2021 15:59] – [Restrictions] Laszlo Nagyresources:fpga:peripherals:jesd204:axi_jesd204_rx [13 Oct 2021 09:00] – Add footer Iulia Moldovan
Line 8: Line 8:
 It has been designed for interoperability with [[#supported_devices|Analog Devices JESD204 ADC converter products]]. It has been designed for interoperability with [[#supported_devices|Analog Devices JESD204 ADC converter products]].
 To form a complete JESD204 receive logic device it has to be combined with a [[.:#physical_layer|PHY layer]] and [[.:#transport_layer|transport layer]] peripheral. To form a complete JESD204 receive logic device it has to be combined with a [[.:#physical_layer|PHY layer]] and [[.:#transport_layer|transport layer]] peripheral.
 +
  
 ===== Features ===== ===== Features =====
Line 22: Line 23:
   * Low Latency   * Low Latency
   * Independent per lane enable/disable   * Independent per lane enable/disable
 +
  
 ===== Utilization ===== ===== Utilization =====
Line 44: Line 46:
 | ::: | 8 | TBD | TBD | | ::: | 8 | TBD | TBD |
 </hidden> </hidden>
 +
 +
 ===== Files ===== ===== Files =====
  
Line 53: Line 57:
  
 {{:resources:fpga:peripherals:jesd204:axi_jesd204_rx_204c.png|axi_jesd204_rx block diagram}} {{:resources:fpga:peripherals:jesd204:axi_jesd204_rx_204c.png|axi_jesd204_rx block diagram}}
- 
- 
- 
- 
- 
  
  
Line 68: Line 67:
 | ''LINK_MODE'' | Decoder selection of the link layer. \\ 1 - 8B/10B mode \\ 2 - 64B/66B mode  | 1 | | ''LINK_MODE'' | Decoder selection of the link layer. \\ 1 - 8B/10B mode \\ 2 - 64B/66B mode  | 1 |
 | ''DATA_PATH_WIDTH '' | Data path width in bytes. \\ Set it 4 in case of 8B/10B, 8 in case of 64B/66B | 4 | | ''DATA_PATH_WIDTH '' | Data path width in bytes. \\ Set it 4 in case of 8B/10B, 8 in case of 64B/66B | 4 |
 +
  
 ===== Signal and Interface Pins ===== ===== Signal and Interface Pins =====
Line 83: Line 83:
 | ''phy_en_char_align'' | Output | Enable transceiver character alignment. | | ''phy_en_char_align'' | Output | Enable transceiver character alignment. |
 | ''phy_ready'' | Input | Transceiver status. | | ''phy_ready'' | Input | Transceiver status. |
 +
  
 ===== Register Map ===== ===== Register Map =====
  
 {{page>:resources:fpga:docs:hdl:regmap##JESD204 RX (axi_jesd204_rx)&nofooter&noeditbtn}} {{page>:resources:fpga:docs:hdl:regmap##JESD204 RX (axi_jesd204_rx)&nofooter&noeditbtn}}
- 
  
 |< 100% 10em 10em >| |< 100% 10em 10em >|
Line 95: Line 95:
 | RW1C | Write-1-to-clear | Reads will return the current register value. Writing the register will clear those bits of the register which were set to 1 in the value written. | | RW1C | Write-1-to-clear | Reads will return the current register value. Writing the register will clear those bits of the register which were set to 1 in the value written. |
 | V | Volatile | The V suffix indicates that the register is volatile and its content might change without software interaction. The value of a non-volatile register will not change without an explicit write done by software. | | V | Volatile | The V suffix indicates that the register is volatile and its content might change without software interaction. The value of a non-volatile register will not change without an explicit write done by software. |
 +
  
 ===== Theory of Operation ===== ===== Theory of Operation =====
Line 101: Line 102:
  
 The register map is used to configure the operational parameters of the link processor as well as to query the current state of the link processor. The link processor itself is responsible for handling the JESD204 link layer protocol. The register map is used to configure the operational parameters of the link processor as well as to query the current state of the link processor. The link processor itself is responsible for handling the JESD204 link layer protocol.
 +
  
 ==== Interfaces and Signals ==== ==== Interfaces and Signals ====
Line 143: Line 145:
  
 <WRAP clear></WRAP> <WRAP clear></WRAP>
 +
  
 ==== Configuration Interface ==== ==== Configuration Interface ====
Line 265: Line 268:
  
 The state of each individual lane can be queried from the [[#lane_status|lane status]] registers. The state of each individual lane can be queried from the [[#lane_status|lane status]] registers.
- 
  
 === Lane Status === === Lane Status ===
Line 289: Line 291:
   * EMB_HUNT (3'b010): Keep track and monitor consecutive EoEMBs until a threshold is reached.    * EMB_HUNT (3'b010): Keep track and monitor consecutive EoEMBs until a threshold is reached. 
   * EMB_LOCK (3'b100): Asserted by receiver to indicate that extended multiblock alignment has been achieved   * EMB_LOCK (3'b100): Asserted by receiver to indicate that extended multiblock alignment has been achieved
- 
  
 === 8B/10B Link ILAS Configuration Data === === 8B/10B Link ILAS Configuration Data ===
Line 302: Line 303:
  
 The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 indicates that the link clock is currently not active. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 indicates that the link clock is currently not active.
 +
  
 ==== Interrupts ==== ==== Interrupts ====
  
 The core does not generates interrupts.  The core does not generates interrupts. 
 +
 +
 ===== 8B/10B Link ===== ===== 8B/10B Link =====
  
 {{ :resources:fpga:peripherals:jesd204:axi_jesd204_rx_204c_8b10b.png?600 | 8b10b link layer block diagram}} {{ :resources:fpga:peripherals:jesd204:axi_jesd204_rx_204c_8b10b.png?600 | 8b10b link layer block diagram}}
 +
  
 ==== 8B/10B Link State Machine ==== ==== 8B/10B Link State Machine ====
Line 351: Line 356:
  
 <WRAP clear></WRAP> <WRAP clear></WRAP>
 +
  
 ===== 64B/66B Link ===== ===== 64B/66B Link =====
Line 360: Line 366:
  
 Beside the CRC errors the error monitor records invalid end of multiblock, end of extended multiblock and invalid sync header errors. The source of every error can be masked from the corresponding bit of the ''LINK_CONF3'' register. Beside the CRC errors the error monitor records invalid end of multiblock, end of extended multiblock and invalid sync header errors. The source of every error can be masked from the corresponding bit of the ''LINK_CONF3'' register.
- 
  
 {{ :resources:fpga:peripherals:jesd204:axi_jesd204_rx_204c_64b66b.png?600 | 64b66b link layer block diagram}} {{ :resources:fpga:peripherals:jesd204:axi_jesd204_rx_204c_64b66b.png?600 | 64b66b link layer block diagram}}
 +
  
 ==== 64B/66B Link State Machine  ==== ==== 64B/66B Link State Machine  ====
Line 415: Line 421:
 <WRAP clear></WRAP> <WRAP clear></WRAP>
  
-==== Diagnostics ==== 
  
 ===== Software Support ===== ===== Software Support =====
Line 422: Line 427:
  
   * [[:resources:tools-software:linux-drivers:jesd204:axi_jesd204_rx|JESD204 Receive Linux Driver Support]]   * [[:resources:tools-software:linux-drivers:jesd204:axi_jesd204_rx|JESD204 Receive Linux Driver Support]]
 +
 +
 ===== Restrictions ===== ===== Restrictions =====
  
Line 435: Line 442:
   * Reduced number of frames-per-multi-frame settings. The following values are supported by the peripheral: 1-32, with the additional requirement that F*K is a multiple of 4. In addition F*K needs to be in the range of 4-256.   * Reduced number of frames-per-multi-frame settings. The following values are supported by the peripheral: 1-32, with the additional requirement that F*K is a multiple of 4. In addition F*K needs to be in the range of 4-256.
   * No support for alignment character replacement when scrambling is disabled. (No longer applies starting from 1.07.a)   * No support for alignment character replacement when scrambling is disabled. (No longer applies starting from 1.07.a)
 +
  
 ===== Additional Information ===== ===== Additional Information =====
  
   * [[..:jesd204:jesd204_glossary|JESD204 Glossary]]   * [[..:jesd204:jesd204_glossary|JESD204 Glossary]]
 +
  
 ===== Supported Devices ===== ===== Supported Devices =====
Line 447: Line 456:
  
 {{page>:resources:fpga:peripherals/jesd204##jesd204bc_mixed-signal_front_ends&nofooter&noeditbtn}} {{page>:resources:fpga:peripherals/jesd204##jesd204bc_mixed-signal_front_ends&nofooter&noeditbtn}}
 +
  
 ===== Technical Support ===== ===== Technical Support =====
Line 452: Line 462:
 Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Clock, etc) via the [[ez>community/fpga|EngineerZone]] under the GPL license. If you would like deterministic support when using this core with an ADI component, please investigate a commercial license. Using a non-ADI JESD204 device with this core is possible under the GPL, but Analog Devices will not help with issues you may Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Clock, etc) via the [[ez>community/fpga|EngineerZone]] under the GPL license. If you would like deterministic support when using this core with an ADI component, please investigate a commercial license. Using a non-ADI JESD204 device with this core is possible under the GPL, but Analog Devices will not help with issues you may
 encounter. encounter.
 +
  
 ===== More Information ===== ===== More Information =====
  
   * [[.|JESD204 High-Speed Serial Interface Support]]   * [[.|JESD204 High-Speed Serial Interface Support]]
 +
 +{{navigation HDL User Guide#../../docs/ip_cores|IP cores#../../docs/hdl|Main page#../../docs/tips|Using and modifying the HDL design}}
resources/fpga/peripherals/jesd204/axi_jesd204_rx.txt · Last modified: 23 Jan 2024 10:40 by Adrian Costina

Page Tools