This version is outdated by a newer approved version.
This version (23 May 2017 10:55) is a draft.
Approvals: 0/1
This version (23 May 2017 10:55) is a draft.Approvals: 0/1
This is an old revision of the document!
Table of Contents
UTIL_VAR_FIFO
The UTIL_VAR_FIFO IP controls an external BRAM memory through which it allows the storage of a variable number of samples before triggering.
Features
- Variable depth
Configuration Parameters
| Name | Description | Default Value |
|---|---|---|
DATA_WIDTH | Data width of the FIFO. The BRAM generator parameters should match this | 32 |
ADDRESS_WIDTH | The BRAM generator parameters should match this. Gives the maximum depth of the FIFO | 13 |
Interface
| Interface | Pin | Type | Description |
|---|---|---|---|
| Clock | |||
clk | input | Clock input. Should be synchronous to the input and the output data | |
| Reset | |||
rst | input | Reset input. Should be synchronous clk clock | |
| Depth | |||
depth | input[31:0] | Controls the depth of the FIFO. Should be less than the maximum depth. Controlled by an outside IP | |
| Data Input | |||
data_in | input[DATA_WIDTH-1:0] | Data to be stored | |
data_in_valid | input[15:0] | Valid for the input data | |
| Data Output | |||
data_out | output[DATA_WIDTH-1:0] | Data forwarded to the DMA | |
data_out_valid | output | Valid for the output data | |
| BRAM Connections | |||
wea_w | output | Write signal | |
en_w | output | Write enable signal | |
addr_w | output[ADDRESS_WIDTH-1:0] | Address to the write pointer | |
din_w | output[DATA_WIDTH-1:0] | Data to be written to the BRAM | |
en_r | output | Read enable signal | |
addr_r | output[ADDRESS_WIDTH-1:0] | Address for the read pointer | |
dout_r | input[DATA_WIDTH-1:0] | Data read from the BRAM | |
Detailed Description
This IP controlls and external BRAM. It has a two clock cycle latency even if bypassed. If valid is not always asserted, the latency is only one word instead of two.
Design Guidelines
The IP should be used with an external BRAM, which can be optimized for power or for speed, depending on the design requirements. It only one clock domain, so everything should be synchonous to that clock domain.
References
Navigation -
resources/fpga/docs/util_var_fifo.1495529736.txt.gz · Last modified: 23 May 2017 10:55 by Adrian Costina