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resources:fpga:docs:util_axis_fifo [11 Oct 2021 14:55] – Edit next page to be Using and modifying the HDL design Iulia Moldovanresources:fpga:docs:util_axis_fifo [12 Oct 2021 16:56] (current) – Edit footer Iulia Moldovan
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-====== AXI Stream FIFO Core (util_axis_fifo) ======+====== AXI Stream FIFO Core ======
  
 The util_axis_fifo IP core is a simple FIFO (First Input First Output) with AXI streaming interfaces, supporting synchronous and asynchronous operation modes. It can be used to mitigate data rate differences or transfer an AXI stream to a different clock domain.  The util_axis_fifo IP core is a simple FIFO (First Input First Output) with AXI streaming interfaces, supporting synchronous and asynchronous operation modes. It can be used to mitigate data rate differences or transfer an AXI stream to a different clock domain. 
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 ===== Features ===== ===== Features =====
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   * Supports FULL/EMPTY and ALMOST_FULL/ALMOST_EMPTY status signals   * Supports FULL/EMPTY and ALMOST_FULL/ALMOST_EMPTY status signals
   * Support zero-deep implementation   * Support zero-deep implementation
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 ===== Functional Description ===== ===== Functional Description =====
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 <note important>In case of asynchronous mode, because of the delays introduced by the clock domain crossing logic, the ROOM and LEVEL indicators can not reflect the actual state of the FIFO in real time. Source and destination logic should take this into account when controlling the data stream into and from the FIFO. Carefully adjusting the ALMOST_EMPTY/ALMOST_FULL indicators can provide a save operating margin.</note> <note important>In case of asynchronous mode, because of the delays introduced by the clock domain crossing logic, the ROOM and LEVEL indicators can not reflect the actual state of the FIFO in real time. Source and destination logic should take this into account when controlling the data stream into and from the FIFO. Carefully adjusting the ALMOST_EMPTY/ALMOST_FULL indicators can provide a save operating margin.</note>
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 ===== Parameters ===== ===== Parameters =====
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 | ''ALMOST_EMPTY_THRESHOLD'' | Defines the offset (in data beats) between the almost empty and empty assertion | 16 | | ''ALMOST_EMPTY_THRESHOLD'' | Defines the offset (in data beats) between the almost empty and empty assertion | 16 |
 | ''ALMOST_FULL_THRESHOLD'' | Defines the offset (in data beats) between the almost full and full assertion | 16 | | ''ALMOST_FULL_THRESHOLD'' | Defines the offset (in data beats) between the almost full and full assertion | 16 |
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 ===== Interface ===== ===== Interface =====
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 | '' m_axis_almost_full '' | output | If set the FIFO is almost full | | '' m_axis_almost_full '' | output | If set the FIFO is almost full |
 | '' m_axis_full '' | output | If set the FIFO is full | | '' m_axis_full '' | output | If set the FIFO is full |
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 ===== Register Map ===== ===== Register Map =====
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 This core does not have a register map. This core does not have a register map.
  
-{{navigation HDL User Guide#axi_ip|AXI IP cores#hdl|Main page#tips|Using and modifying the HDL design}}+{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/util_axis_fifo.txt · Last modified: 12 Oct 2021 16:56 by Iulia Moldovan

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