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resources:fpga:docs:hdl:regmap [08 Sep 2023 15:41] – [DAC Channel (axi_ad*)] Updated HDL Doc Cristian Mihai Poparesources:fpga:docs:hdl:regmap [19 Feb 2024 13:35] (current) – [PWM Generator (axi_pwm_gen)] Quick register fixes Adrian Costina
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 ==== Base (common to all cores) ==== ==== Base (common to all cores) ====
  
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 |Address ||Bits |Name |Type |Default |Description | |Address ||Bits |Name |Type |Default |Description |
 |DWORD |BYTE |::: |::: |::: |::: |::: | |DWORD |BYTE |::: |::: |::: |::: |::: |
-^0x000 ^0x0000 ^VERSION ^^^^Version of the peripheral. Follows semantic versioning. Current version 4.04.61. ^+^0x000 ^0x0000 ^VERSION ^^^^Version of the peripheral. Follows semantic versioning. Current version 4.05.61. ^
 | | |[31:16] |VERSION_MAJOR |RO |0x04 | | | | |[31:16] |VERSION_MAJOR |RO |0x04 | |
-|::: |::: |[15:8] |VERSION_MINOR |RO |0x03 | |+|::: |::: |[15:8] |VERSION_MINOR |RO |0x05 | |
 |::: |::: |[7:0] |VERSION_PATCH |RO |0x61 | | |::: |::: |[7:0] |VERSION_PATCH |RO |0x61 | |
 ^0x001 ^0x0004 ^PERIPHERAL_ID ^^^^ ^ ^0x001 ^0x0004 ^PERIPHERAL_ID ^^^^ ^
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 |::: |::: |[0] |TRANSFER_QUEUED |RO |0x0 |This bit will be asserted if a transfer has been queued and it is possible to queue the next transfer. Cleared together with the corresponding IRQ_PENDING bit. | |::: |::: |[0] |TRANSFER_QUEUED |RO |0x0 |This bit will be asserted if a transfer has been queued and it is possible to queue the next transfer. Cleared together with the corresponding IRQ_PENDING bit. |
 ^0x100 ^0x0400 ^CONTROL ^^^^ ^ ^0x100 ^0x0400 ^CONTROL ^^^^ ^
-| | |[1] |PAUSE |RW |0x0 |When set to 1 the currently active transfer is paused. It will be resumed once the bit is cleared again. |+| | |[2] |HWDESC |RW |0x0 |When set to 1 the scatter-gather transfers are enabled.  Note, this field is only valid if the DMA channel has been configured with SG transfer support. | 
 +|::: |::: |[1] |PAUSE |RW |0x0 |When set to 1 the currently active transfer is paused. It will be resumed once the bit is cleared again. |
 |::: |::: |[0] |ENABLE |RW |0x0 |When set to 1 the DMA channel is enabled. | |::: |::: |[0] |ENABLE |RW |0x0 |When set to 1 the DMA channel is enabled. |
 ^0x101 ^0x0404 ^TRANSFER_ID ^^^^ ^ ^0x101 ^0x0404 ^TRANSFER_ID ^^^^ ^
 | | |[1:0] |TRANSFER_ID |RO |0x00 |This register contains the ID of the next transfer. The ID is generated by the DMAC and after the transfer has been started can be used to check if the transfer has finished by checking the corresponding bit in the TRANSFER_DONE register. The contents of this register is only valid if TRANSFER_SUBMIT is 0. | | | |[1:0] |TRANSFER_ID |RO |0x00 |This register contains the ID of the next transfer. The ID is generated by the DMAC and after the transfer has been started can be used to check if the transfer has finished by checking the corresponding bit in the TRANSFER_DONE register. The contents of this register is only valid if TRANSFER_SUBMIT is 0. |
 ^0x102 ^0x0408 ^TRANSFER_SUBMIT ^^^^ ^ ^0x102 ^0x0408 ^TRANSFER_SUBMIT ^^^^ ^
-| | |[0] |TRANSFER_SUBMIT |RW |0x00 |Writing a 1 to this register queues a new transfer. The bit transitions back to 0 once the transfer has been queued or the DMA channel is disabled.  Writing a 0 to this register has no effect. |+| | |[0] |TRANSFER_SUBMIT |RW |0x0 |Writing a 1 to this register queues a new transfer. The bit transitions back to 0 once the transfer has been queued or the DMA channel is disabled.  Writing a 0 to this register has no effect. |
 ^0x103 ^0x040c ^FLAGS ^^^^ ^ ^0x103 ^0x040c ^FLAGS ^^^^ ^
 | | |[0] |CYCLIC |RW |''CYCLIC'' |Setting this field to 1 puts the DMA transfer into cyclic mode. In cyclic mode the controller will re-start a transfer again once it has finished. In cyclic mode no end-of-transfer interrupts will be generated. | | | |[0] |CYCLIC |RW |''CYCLIC'' |Setting this field to 1 puts the DMA transfer into cyclic mode. In cyclic mode the controller will re-start a transfer again once it has finished. In cyclic mode no end-of-transfer interrupts will be generated. |
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 | | |[4:0] |ACTIVE_TRANSFER_ID |RO |0x00 |ID of the currently active transfer. When no transfer is active this register will be equal to the TRANSFER_ID register. | | | |[4:0] |ACTIVE_TRANSFER_ID |RO |0x00 |ID of the currently active transfer. When no transfer is active this register will be equal to the TRANSFER_ID register. |
 ^0x10c ^0x0430 ^STATUS ^^^^ ^ ^0x10c ^0x0430 ^STATUS ^^^^ ^
-| | |[31:0] |RESERVED |RO |0x00 |This register is reserved for future usage. Reading it will always return 0. |+| | |[31:0] |RESERVED |RO |0x00000000 |This register is reserved for future usage. Reading it will always return 0. |
 ^0x10d ^0x0434 ^CURRENT_DEST_ADDRESS ^^^^ ^ ^0x10d ^0x0434 ^CURRENT_DEST_ADDRESS ^^^^ ^
-| | |[31:0] |CURRENT_DEST_ADDRESS |RO |0x00 |Address to which the next data sample is written to.  This register is only valid if the DMA channel has been configured for write to memory support. |+| | |[31:0] |CURRENT_DEST_ADDRESS |RO |0x00000000 |Address to which the next data sample is written to.  This register is only valid if the DMA channel has been configured for write to memory support. |
 ^0x10e ^0x0438 ^CURRENT_SRC_ADDRESS ^^^^ ^ ^0x10e ^0x0438 ^CURRENT_SRC_ADDRESS ^^^^ ^
-| | |[31:0] |CURRENT_SRC_ADDRESS |RO |0x00 |Address form which the next data sample is read.  This register is only valid if the DMA channel has been configured for read from memory support. |+| | |[31:0] |CURRENT_SRC_ADDRESS |RO |0x00000000 |Address form which the next data sample is read.  This register is only valid if the DMA channel has been configured for read from memory support. |
 ^0x112 ^0x0448 ^TRANSFER_PROGRESS ^^^^ ^ ^0x112 ^0x0448 ^TRANSFER_PROGRESS ^^^^ ^
 | | |[23:0] |TRANSFER_PROGRESS |RO |0x000000 |This field presents the number of bytes transferred to the destination for the current transfer. This register will be cleared once the transfer completes. This should be used for debugging purposes only. | | | |[23:0] |TRANSFER_PROGRESS |RO |0x000000 |This field presents the number of bytes transferred to the destination for the current transfer. This register will be cleared once the transfer completes. This should be used for debugging purposes only. |
 ^0x113 ^0x044c ^PARTIAL_TRANSFER_LENGTH ^^^^ ^ ^0x113 ^0x044c ^PARTIAL_TRANSFER_LENGTH ^^^^ ^
-| | |[31:0] |PARTIAL_LENGTH |RO |0x000000 |Length of the partial transfer in bytes. Represents the number of bytes received until the moment of TLAST assertion. This will be smaller than the programmed length from the X_LENGTH and Y_LENGTH registers. |+| | |[31:0] |PARTIAL_LENGTH |RO |0x00000000 |Length of the partial transfer in bytes. Represents the number of bytes received until the moment of TLAST assertion. This will be smaller than the programmed length from the X_LENGTH and Y_LENGTH registers. |
 ^0x114 ^0x0450 ^PARTIAL_TRANSFER_ID ^^^^Must be read after the PARTIAL_TRANSFER_LENGTH registers. ^ ^0x114 ^0x0450 ^PARTIAL_TRANSFER_ID ^^^^Must be read after the PARTIAL_TRANSFER_LENGTH registers. ^
 | | |[1:0] |PARTIAL_TRANSFER_ID |RO |0x0 |ID of the transfer that was partial.  | | | |[1:0] |PARTIAL_TRANSFER_ID |RO |0x0 |ID of the transfer that was partial.  |
 +^0x115 ^0x0454 ^DESCRIPTOR_ID ^^^^ ^
 +| | |[31:0] |DESCRIPTOR_ID |RO |0x00000000 |ID of the descriptor that points to the current memory segment being transferred. If HWDESC is set to 0, then this register returns 0.  |
 +^0x11f ^0x047c ^SG_ADDRESS ^^^^ ^
 +| | |[31:0] |SG_ADDRESS |RW |0x00000000 |This register contains the starting address of the scatter-gather transfer. The address needs to be aligned to the bus width.  This register is only valid if the DMA channel has been configured with SG transfer support. |
 ^0x124 ^0x0490 ^DEST_ADDRESS_HIGH ^^^^ ^ ^0x124 ^0x0490 ^DEST_ADDRESS_HIGH ^^^^ ^
 | | |[31:0] |DEST_ADDRESS_HIGH |RW |0x00000000 |This register contains the HIGH segment of the destination address of the transfer.  This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if DMA channel has been configured for write to memory support. | | | |[31:0] |DEST_ADDRESS_HIGH |RW |0x00000000 |This register contains the HIGH segment of the destination address of the transfer.  This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if DMA channel has been configured for write to memory support. |
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 | | |[31:0] |SRC_ADDRESS_HIGH |RW |0x00000000 |This register contains the HIGH segment of the source address of the transfer.  This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support. | | | |[31:0] |SRC_ADDRESS_HIGH |RW |0x00000000 |This register contains the HIGH segment of the source address of the transfer.  This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support. |
 ^0x126 ^0x0498 ^CURRENT_DEST_ADDRESS_HIGH ^^^^ ^ ^0x126 ^0x0498 ^CURRENT_DEST_ADDRESS_HIGH ^^^^ ^
-| | |[31:0] |CURRENT_DEST_ADDRESS_HIGH |RO |0x00 |HIGH segment of the address to which the next data sample is written to.  This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for write to memory support. |+| | |[31:0] |CURRENT_DEST_ADDRESS_HIGH |RO |0x00000000 |HIGH segment of the address to which the next data sample is written to.  This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for write to memory support. |
 ^0x127 ^0x049c ^CURRENT_SRC_ADDRESS_HIGH ^^^^ ^ ^0x127 ^0x049c ^CURRENT_SRC_ADDRESS_HIGH ^^^^ ^
-| | |[31:0] |CURRENT_SRC_ADDRESS_HIGH |RO |0x00 |HIGH segment of the address from which the next data sample is read.  This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support. | +| | |[31:0] |CURRENT_SRC_ADDRESS_HIGH |RO |0x00000000 |HIGH segment of the address from which the next data sample is read.  This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support. | 
-^Tue Mar 14 10:17:59 2023 ^^^^^^+^0x12f ^0x04bc ^SG_ADDRESS_HIGH ^^^^ ^ 
 +| | |[31:0] |SG_ADDRESS_HIGH |RW |0x00000000 |HIGH segment of the starting address of the scatter-gather transfer.  This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured with SG transfer support. | 
 +^Thu Feb  1 12:18:03 2024 ^^^^^^
 ++++ ++++
  
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 |DWORD |BYTE |::: |::: |::: |::: |::: | |DWORD |BYTE |::: |::: |::: |::: |::: |
 ^0x0000 ^0x0000 ^REG_VERSION ^^^^Version and Scratch Registers ^ ^0x0000 ^0x0000 ^REG_VERSION ^^^^Version and Scratch Registers ^
-| | |[31:0] |VERSION[31:0] |RO |0x00010100 |Version number. Unique to all cores. |+| | |[31:0] |VERSION[31:0] |RO |0x00020000 |Version number. Unique to all cores. |
 ^0x0001 ^0x0004 ^REG_ID ^^^^Core ID ^ ^0x0001 ^0x0004 ^REG_ID ^^^^Core ID ^
 | | |[31:0] |ID[31:0] |RO |0x00000000 |Instance identifier number. | | | |[31:0] |ID[31:0] |RO |0x00000000 |Instance identifier number. |
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 | | |[31:0] |SCRATCH[31:0] |RW |0x00000000 |Scratch register. | | | |[31:0] |SCRATCH[31:0] |RW |0x00000000 |Scratch register. |
 ^0x0003 ^0x000c ^REG_CORE_MAGIC ^^^^Identification number ^ ^0x0003 ^0x000c ^REG_CORE_MAGIC ^^^^Identification number ^
-| | |[31:0] |CORE_MAGIC[31:0] |RW |0x504C5347 |Identification number. |+| | |[31:0] |CORE_MAGIC[31:0] |RW |0x601A3471 |Identification number. |
 ^0x0004 ^0x0010 ^REG_RSTN ^^^^Reset and load values ^ ^0x0004 ^0x0010 ^REG_RSTN ^^^^Reset and load values ^
 | | |[1] |LOAD_CONFIG |WO |0x0 |Loads the new values written in the config registers. | | | |[1] |LOAD_CONFIG |WO |0x0 |Loads the new values written in the config registers. |
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 ^0x0005 ^0x0014 ^REG_NB_PULSES ^^^^Number of pulses ^ ^0x0005 ^0x0014 ^REG_NB_PULSES ^^^^Number of pulses ^
 | | |[31:0] |NB_PULSES |RO |0x0000 |Number of configurable pulses. | | | |[31:0] |NB_PULSES |RO |0x0000 |Number of configurable pulses. |
-^0x0010 ^0x0040 ^REG_PULSE_0_PERIOD ^^^^Pulse 0 period ^ +^0x0010 ^0x0040 ^REG_PULSE_X_PERIOD ^^^^Pulse x period ^ 
-| | |[31:0] |PULSE_0_PERIOD[31:0] |RW |0x0000 |Pulse 0 duration, defined in number of clock cycles. | +| | |[31:0] |PULSE_X_PERIOD[31:0] - base + 'h4 for each channel -> e.g. CH3 period - 'h4C|RW |0x0000 |Pulse x duration, defined in number of clock cycles. | 
-^0x0011 ^0x0044 ^REG_PULSE_0_WIDTH ^^^^Pulse 0 width ^ +^0x0020 ^0x0080 ^REG_PULSE_X_WIDTH ^^^^Pulse x width ^ 
-| | |[31:0] |PULSE_0_WIDTH[31:0] |RW |0x0000 |Pulse 0 width (high time), defined in number of clock cycles. | +| | |[31:0] |PULSE_X_WIDTH[31:0] - base + 'h4 for each channel -> e.g. CH3 width - 'h8C|RW |0x0000 |Pulse x width (high time), defined in number of clock cycles. | 
-^0x0012 ^0x0048 ^REG_PULSE_0_OFFSET ^^^^Pulse 0 offset ^ +^0x0030 ^0x00C0 ^REG_PULSE_X_OFFSET ^^^^Pulse x offset ^ 
-| | |[31:0] |PULSE_0_OFFSET[31:0] |RW |0x0000 |Pulse 0 offset, defined in number of clock cycles. | +| | |[31:0] |PULSE_X_OFFSET[31:0] - base + 'h4 for each channel -> e.g. CH3 offset - 'hCC|RW |0x0000 |Pulse x offset, defined in number of clock cycles. | 
-^0x0013 ^0x004c ^REG_PULSE_1_PERIOD ^^^^Pulse 1 period ^ +
-| | |[31:0] |PULSE_1_PERIOD[31:0] |RW |0x0000 |Pulse 1 duration, defined in number of clock cycles. | +
-^0x0014 ^0x0050 ^REG_PULSE_1_WIDTH ^^^^Pulse 1 width ^ +
-| | |[31:0] |PULSE_1_WIDTH[31:0] |RW |0x0000 |Pulse 1 width (high time), defined in number of clock cycles. | +
-^0x0015 ^0x0054 ^REG_PULSE_1_OFFSET ^^^^Pulse 1 offset ^ +
-| | |[31:0] |PULSE_1_OFFSET[31:0] |RW |0x0000 |Pulse 1 offset, defined in number of clock cycles. | +
-^0x0016 ^0x0058 ^REG_PULSE_2_PERIOD ^^^^Pulse 2 period ^ +
-| | |[31:0] |PULSE_2_PERIOD[31:0] |RW |0x0000 |Pulse 2 duration, defined in number of clock cycles. | +
-^0x0017 ^0x005c ^REG_PULSE_2_WIDTH ^^^^Pulse 2 width ^ +
-| | |[31:0] |PULSE_2_WIDTH[31:0] |RW |0x0000 |Pulse 2 width (high time) defined in number of clock cycles. | +
-^0x0018 ^0x0060 ^REG_PULSE_2_OFFSET ^^^^Pulse 2 offset ^ +
-| | |[31:0] |PULSE_2_OFFSET[31:0] |RW |0x0000 |Pulse 2 offset, defined in number of clock cycles. | +
-^0x0019 ^0x0064 ^REG_PULSE_3_PERIOD ^^^^Pulse 3 period ^ +
-| | |[31:0] |PULSE_3_PERIOD[31:0] |RW |0x0000 |Pulse 3 duration, defined in number of clock cycles. | +
-^0x001a ^0x0068 ^REG_PULSE_3_WIDTH ^^^^Pulse 3 width ^ +
-| | |[31:0] |PULSE_3_WIDTH[31:0] |RW |0x0000 |Pulse 3 width (high time) defined in number of clock cycles. | +
-^0x001b ^0x006c ^REG_PULSE_3_OFFSET ^^^^Pulse 3 offset ^ +
-| | |[31:0] |PULSE_3_OFFSET[31:0] |RW |0x0000 |Pulse 3 offset, defined in number of clock cycles. | +
-^Tue Mar 14 10:17:59 2023 ^^^^^^+
 ++++ ++++
 ~~NOTOC~~ ~~NOTOC~~
  
  
resources/fpga/docs/hdl/regmap.1694180488.txt.gz · Last modified: 08 Sep 2023 15:41 by Cristian Mihai Popa

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