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This version (19 Feb 2024 13:35) was approved by Adrian Costina.The Previously approved version (01 Feb 2024 11:52) is available.

Base (common to all cores)

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0x0000	0x0000	REG_VERSION				Version and Scratch Registers
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:0]	VERSION[31:0]	RO	0x00000000	Version number. Unique to all cores.
0x0001	0x0004	REG_ID				Version and Scratch Registers
		[31:0]	ID[31:0]	RO	0x00000000	Instance identifier number.
0x0002	0x0008	REG_SCRATCH				Version and Scratch Registers
		[31:0]	SCRATCH[31:0]	RW	0x00000000	Scratch register.
0x0003	0x000c	REG_CONFIG				Version and Scratch Registers
		[0]	IQCORRECTION_DISABLE	RO	0x0	If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)
		[1]	DCFILTER_DISABLE	RO	0x0	If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)
		[2]	DATAFORMAT_DISABLE	RO	0x0	If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)
		[3]	USERPORTS_DISABLE	RO	0x0	If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)
		[4]	MODE_1R1T	RO	0x0	If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)
		[5]	DELAY_CONTROL_DISABLE	RO	0x0	If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)
		[6]	DDS_DISABLE	RO	0x0	If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)
		[7]	CMOS_OR_LVDS_N	RO	0x0	CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)
		[8]	PPS_RECEIVER_ENABLE	RO	0x0	If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)
		[9]	SCALECORRECTION_ONLY	RO	0x0	If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance)
		[12]	EXT_SYNC	RO	0x0	If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.
		[13]	RD_RAW_DATA	RO	0x0	If set, the ADC has the capability to read raw data in register REG_CHAN_RAW_DATA from adc_channel.
0x0004	0x0010	REG_PPS_IRQ_MASK				PPS Interrupt mask
		[0]	PPS_IRQ_MASK	RW	0x1	Mask bit for the 1PPS receiver interrupt
0x0007	0x001c	REG_FPGA_INFO				FPGA device information Intel encoded values Xilinx encoded values
		[31:24]	FPGA_TECHNOLOGY	RO	0x0	Encoded value describing the technology/generation of the FPGA device (arria 10/7series)
		[23:16]	FPGA_FAMILY	RO	0x0	Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)
		[15:8]	SPEED_GRADE	RO	0x0	Encoded value describing the FPGA's speed-grade
		[7:0]	DEV_PACKAGE	RO	0x0	Encoded value describing the device package. The package might affect high-speed interfaces
Tue Mar 14 10:17:59 2023

ADC Common (axi_ad*)

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0x0010	0x0040	REG_RSTN				ADC Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[2]	CE_N	RW	0x0	Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables
		[1]	MMCM_RSTN	RW	0x0	MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
		[0]	RSTN	RW	0x0	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x0011	0x0044	REG_CNTRL				ADC Interface Control & Status
		[16]	SDR_DDR_N	RW	0x0	Interface type (1 represents SDR, 0 represents DDR)
		[15]	SYMB_OP	RW	0x0	Select symbol data format mode (0x1)
		[14]	SYMB_8_16B	RW	0x0	Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
		[12:8]	NUM_LANES[4:0]	RW	0x0	Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane). For AD7768, AD7768-4 and AD777x number of active lanes : 1/2/4/8 where supported.
		[3]	SYNC	RW	0x0	Initialize synchronization between multiple ADCs
		[2]	R1_MODE	RW	0x0	Select number of RF channels 1 (0x1) or 2 (0x0).
		[1]	DDR_EDGESEL	RW	0x0	Select rising edge (0x0) or falling edge (0x1) for the first part of a sample (if applicable) followed by the successive edges for the remaining parts. This only controls how the sample is delineated from the incoming data post DDR registers.
		[0]	PIN_MODE	RW	0x0	Select interface pin mode to be clock multiplexed (0x1) or pin multiplexed (0x0). In clock multiplexed mode, samples are received on alternative clock edges. In pin multiplexed mode, samples are interleaved or grouped on the pins at the same clock edge.
0x0012	0x0048	REG_CNTRL_2				ADC Interface Control & Status
		[1]	EXT_SYNC_ARM	RW	0x0	Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
		[2]	EXT_SYNC_DISARM	RW	0x0	Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
		[8]	MANUAL_SYNC_REQUEST	RW	0x0	Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
0x0013	0x004c	REG_CNTRL_3				ADC Interface Control & Status
		[8]	CRC_EN	RW	0x0	Setting this bit will enable the CRC generation.
		[7:0]	CUSTOM_CONTROL	RW	0x00	ADAQ8092 Select output format decode mode. - bit [0] - enables digital output randomizer decode - bit [1] - enables alternate bit polarity decode AD4858 Select data format/oversampling - bit [2] - enable oversampling - bits [1:0] packet format selection: 0 = 20 bit 1 = 24 bit 2 = 32 bit 3 = 32 bit AD7606X_PI Select the parallel interface's operation mode - bit [2] - change mode with the selected one - bits [1:0] - requested operation mode: 0 = SIMPLE 1 = CRC_ENABLED 2 = STATUS_HEADER 3 = CRC_STATUS 07 Mar 2023 17:38 · Andrei Grozav
0x0015	0x0054	REG_CLK_FREQ				ADC Interface Control & Status
		[31:0]	CLK_FREQ[31:0]	RO	0x0000	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016	0x0058	REG_CLK_RATIO				ADC Interface Control & Status
		[31:0]	CLK_RATIO[31:0]	RO	0x0000	Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0017	0x005c	REG_STATUS				ADC Interface Control & Status
		[4]	ADC_CTRL_STATUS	RO	0x0	If set, indicates that the device's register data is available on the data bus.
		[3]	PN_ERR	RO	0x0	If set, indicates pn error in one or more channels.
		[2]	PN_OOS	RO	0x0	If set, indicates pn oos in one or more channels.
		[1]	OVER_RANGE	RO	0x0	If set, indicates over range in one or more channels.
		[0]	STATUS	RO	0x0	Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018	0x0060	REG_DELAY_CNTRL				ADC Interface Control & Status(`Deprecated from version 9`)
		[17]	DELAY_SEL	RW	0x0	Delay select, a 0x0 to 0x1 transition in this register initiates a delay access controlled by the registers below.
		[16]	DELAY_RWN	RW	0x0	Delay read (0x1) or write (0x0), the delay is accessed directly (no increment or decrement) with an address corresponding to each pin, and data corresponding to the total delay.
		[15:8]	DELAY_ADDRESS[7:0]	RW	0x00	Delay address, the range depends on the interface pins, data pins are usually at the lower range.
		[4:0]	DELAY_WDATA[4:0]	RW	0x0	Delay write data, a value of 1 corresponds to (1/200)ns for most devices.
0x0019	0x0064	REG_DELAY_STATUS				ADC Interface Control & Status(`Deprecated from version 9`)
		[9]	DELAY_LOCKED	RO	0x0	Indicates delay locked (0x1) state. If this bit is read 0x0, delay control has failed to calibrate the elements.
		[8]	DELAY_STATUS	RO	0x0	If set, indicates busy status (access pending). The read data may not be valid if this bit is set.
		[4:0]	DELAY_RDATA[4:0]	RO	0x0	Delay read data, current delay value in the elements
0x001A	0x0068	REG_SYNC_STATUS				ADC Synchronization Status register
		[0]	ADC_SYNC	RO	0x0	ADC synchronization status. Will be set to 1 after the synchronization has been completed or while waiting for the synchronization signal in JESD204 systems.
0x001C	0x0070	REG_DRP_CNTRL				ADC Interface Control & Status
		[28]	DRP_RWN	RW	0x0	DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[27:16]	DRP_ADDRESS[11:0]	RW	0x00	DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[15:0]	RESERVED[15:0]	RO	0x0000	Reserved for backward compatibility.
0x001D	0x0074	REG_DRP_STATUS				ADC Interface Control & Status
		[17]	DRP_LOCKED	RO	0x0	If set indicates that the DRP has been locked.
		[16]	DRP_STATUS	RO	0x0	If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[15:0]	RESERVED[15:0]	RO	0x00	Reserved for backward compatibility.
0x001E	0x0078	REG_DRP_WDATA				ADC DRP Write Data
		[15:0]	DRP_WDATA[15:0]	RW	0x00	DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x001F	0x007c	REG_DRP_RDATA				ADC DRP Read Data
		[15:0]	DRP_RDATA[15:0]	RO	0x00	DRP read data (does not include GTX lanes).
0x0020	0x0080	REG_ADC_CONFIG_WR				ADC Write Configuration Data
		[31:0]	ADC_CONFIG_WR[31:0]	RW	0x0000	Custom Write to the available registers.
0x0021	0x0084	REG_ADC_CONFIG_RD				ADC Read Configuration Data
		[31:0]	ADC_CONFIG_RD[31:0]	RO	0x0000	Custom read of the available registers.
0x0022	0x0088	REG_UI_STATUS				User Interface Status
		[2]	UI_OVF	RW1C	0x0	User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
		[1]	UI_UNF	RW1C	0x0	User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
		[0]	UI_RESERVED	RW1C	0x0	Reserved for backward compatibility.
0x0023	0x008c	REG_ADC_CONFIG_CTRL				ADC RD/WR configuration
		[31:0]	ADC_CONFIG_CTRL[31:0]	RW	0x0000	Control RD/WR requests to the device's register map: bit 1 - RD ('b1) , WR ('b0), bit 0 - enable WR/RD operation.
0x0028	0x00a0	REG_USR_CNTRL_1				ADC Interface Control & Status
		[7:0]	USR_CHANMAX[7:0]	RW	0x00	This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules post data capture as another input to this common multiplexer. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0029	0x00a4	REG_ADC_START_CODE				ADC Synchronization start word
		[31:0]	ADC_START_CODE[31:0]	RW	0x00000000	This sets the startcode that is used by the ADCs for synchronization NOT-APPLICABLE if START_CODE_DISABLE is set (0x1).
0x002E	0x00b8	REG_ADC_GPIO_IN				ADC GPIO inputs
		[31:0]	ADC_GPIO_IN[31:0]	RO	0x00000000	This reads auxiliary GPI pins of the ADC core
0x002F	0x00bc	REG_ADC_GPIO_OUT				ADC GPIO outputs
		[31:0]	ADC_GPIO_OUT[31:0]	RW	0x00000000	This controls auxiliary GPO pins of the ADC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).
0x0030	0x00c0	REG_PPS_COUNTER				PPS Counter register
		[31:0]	PPS_COUNTER[31:0]	RO	0x00000000	Counts the core clock cycles (can be a device clock or interface clock) between two 1PPS pulse.
0x0031	0x00c4	REG_PPS_STATUS				PPS Status register
		[0]	PPS_STATUS	RO	0x0	If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it's not active.
Fri Aug 11 18:29:53 2023

ADC Channel (axi_ad*)

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0x0100	0x0400	REG_CHAN_CNTRL				ADC Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[11]	ADC_LB_OWR	RW	0x0	If set, forces ADC_DATA_SEL to 1, enabling data loopback
		[10]	ADC_PN_SEL_OWR	RW	0x0	If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361) If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored
		[9]	IQCOR_ENB	RW	0x0	if set, enables IQ correction or scale correction. NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
		[8]	DCFILT_ENB	RW	0x0	if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
		[6]	FORMAT_SIGNEXT	RW	0x0	if set, enables sign extension (applicable only in 2's complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
		[5]	FORMAT_TYPE	RW	0x0	Select offset binary (0x1) or 2's complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
		[4]	FORMAT_ENABLE	RW	0x0	Enable data format conversion (see register bits above). NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
		[3]	RESERVED	RO	0x0	Reserved for backward compatibility.
		[2]	RESERVED	RO	0x0	Reserved for backward compatibility.
		[1]	ADC_PN_TYPE_OWR	RW	0x0	If set, forces ADC_PN_SEL to 0x1, modified pn23 If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored
		[0]	ENABLE	RW	0x0	If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected.
0x0101	0x0404	REG_CHAN_STATUS				ADC Interface Control & Status
		[12]	CRC_ERR	RW1C	0x0	CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards.
		[11:4]	STATUS_HEADER	RO	0x00	The status header sent by the ADC.(compatible with AD7768/AD7768-4/AD777x).
		[2]	PN_ERR	RW1C	0x0	PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared.
		[1]	PN_OOS	RW1C	0x0	PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern.
		[0]	OVER_RANGE	RW1C	0x0	If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards.
0x0102	0x0408	REG_CHAN_RAW_DATA				ADC Raw Data Reading
		[31:0]	ADC_READ_DATA[31:0]	RO	0x0000	Raw data read from the ADC.
0x0104	0x0410	REG_CHAN_CNTRL_1				ADC Interface Control & Status
		[31:16]	DCFILT_OFFSET[15:0]	RW	0x0000	DC removal (if equipped) offset. This is a 2's complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
		[15:0]	DCFILT_COEFF[15:0]	RW	0x0000	DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
0x0105	0x0414	REG_CHAN_CNTRL_2				ADC Interface Control & Status
		[31:16]	IQCOR_COEFF_1[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel with the format 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
		[15:0]	IQCOR_COEFF_2[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
0x0106	0x0418	REG_CHAN_CNTRL_3				ADC Interface Control & Status
		[19:16]	ADC_PN_SEL[3:0]	RW	0x0	Selects the PN monitor sequence type (available only if ADC supports it). - 0x0: pn9a (device specific, modified pn9) - 0x1: pn23a (device specific, modified pn23) - 0x4: pn7 (standard O.150) - 0x5: pn15 (standard O.150) - 0x6: pn23 (standard O.150) - 0x7: pn31 (standard O.150) - 0x9: pnX (device specific, e.g. ad9361) - 0x0A: Nibble ramp (Device specific e.g. adrv9001) - 0x0B: 16 bit ramp (Device specific e.g. adrv9001)
		[3:0]	ADC_DATA_SEL[3:0]	RW	0x0	Selects the data source to DMA. 0x0: input data (ADC) 0x1: loopback data (DAC)
0x0108	0x0420	REG_CHAN_USR_CNTRL_1				ADC Interface Control & Status
		[25]	USR_DATATYPE_BE	RO	0x0	The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[24]	USR_DATATYPE_SIGNED	RO	0x0	The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[23:16]	USR_DATATYPE_SHIFT[7:0]	RO	0x00	The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[15:8]	USR_DATATYPE_TOTAL_BITS[7:0]	RO	0x00	The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[7:0]	USR_DATATYPE_BITS[7:0]	RO	0x00	The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0109	0x0424	REG_CHAN_USR_CNTRL_2				ADC Interface Control & Status
		[31:16]	USR_DECIMATION_M[15:0]	RW	0x0000	This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[15:0]	USR_DECIMATION_N[15:0]	RW	0x0000	This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0110	0x0440	REG_*				Channel 1, similar to register 0x100 to 0x10f.
0x0120	0x0480	REG_*				Channel 2, similar to register 0x100 to 0x10f.
0x01F0	0x07c0	REG_*				Channel 15, similar to register 0x100 to 0x10f.
Tue Mar 14 10:17:59 2023

IO Delay Control (axi_ad*)

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0x00	0x0000	REG_DELAY_CONTROL_0				Delay Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[4:0]	DELAY_CONTROL_IO_0	RW	0x00	Tap value for input/output delay primitive of the first interface line. If the delay controller is not locked (indicate issues with delay_clk), the read-back value of this register will be 0xFFFFFFFF. Otherwise will be the last set up value.
0x01	0x0004	REG_DELAY_CONTROL_1				Delay Control & Status
		[4:0]	DELAY_CONTROL_IO_1	RW	0x00	Tap value for input/output delay primitive of the second interface line. If the delay controller is not locked (indicate issues with delay_clk), the read-back value of this register will be 0xFFFFFFFF. Otherwise will be the last set up value.
0x02	0x0008	REG_*				Tap value for input/output delay primitive of the third interface line.
0x03	0x000c	REG_*				Tap value for input/output delay primitive of the fourth interface line.
0x0F	0x003c	REG_DELAY_CONTROL_F				Delay Control & Status
		[4:0]	DELAY_CONTROL_IO_F	RW	0x00	Tap value for input/output delay primitive of the last interface line. In general the data and frame lines are controlled with delay primitives, the number of registers of a controller is device specific.
Tue Mar 14 10:17:59 2023

DAC Common (axi_ad)

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0x0010	0x0040	REG_RSTN				DAC Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[2]	CE_N	RW	0x0	Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables
		[1]	MMCM_RSTN	RW	0x0	MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
		[0]	RSTN	RW	0x0	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x0011	0x0044	REG_CNTRL_1				DAC Interface Control & Status
		[0]	SYNC	RW	0x0	Setting this bit synchronizes channels within a DAC, and across multiple instances. This bit self clears.
		[1]	EXT_SYNC_ARM	RW	0x0	Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
		[2]	EXT_SYNC_DISARM	RW	0x0	Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
		[8]	MANUAL_SYNC_REQUEST	RW	0x0	Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
0x0012	0x0048	REG_CNTRL_2				DAC Interface Control & Status
		[16]	SDR_DDR_N	RW	0x0	Interface type (1 represents SDR, 0 represents DDR)
		[15]	SYMB_OP	RW	0x0	Select data symbol format mode (0x1)
		[14]	SYMB_8_16B	RW	0x0	Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
		[12:8]	NUM_LANES[4:0]	RW	0x0	Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)
		[7]	PAR_TYPE	RW	0x0	Select parity even (0x0) or odd (0x1).
		[6]	PAR_ENB	RW	0x0	Select parity (0x1) or frame (0x0) mode.
		[5]	R1_MODE	RW	0x0	Select number of RF channels 1 (0x1) or 2 (0x0).
		[4]	DATA_FORMAT	RW	0x0	Select data format 2's complement (0x0) or offset binary (0x1). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
		[3:0]	RESERVED[3:0]	NA	0x00	Reserved
0x0013	0x004c	REG_RATECNTRL				DAC Interface Control & Status
		[7:0]	RATE[7:0]	RW	0x00	The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock.
0x0014	0x0050	REG_FRAME				DAC Interface Control & Status
		[0]	FRAME	RW	0x0	The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1 DCI clock period) pulse on the interface. This bit self clears.
0x0015	0x0054	REG_STATUS1				DAC Interface Control & Status
		[31:0]	CLK_FREQ[31:0]	RO	0x00000000	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016	0x0058	REG_STATUS2				DAC Interface Control & Status
		[31:0]	CLK_RATIO[31:0]	RO	0x00000000	Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0017	0x005c	REG_STATUS3				DAC Interface Control & Status
		[0]	STATUS	RO	0x0	Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018	0x0060	REG_DAC_CLKSEL				DAC Interface Control & Status
		[0]	DAC_CLKSEL	RW	0x0	Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL
0x001A	0x0068	REG_SYNC_STATUS				DAC Synchronization Status register
		[0]	DAC_SYNC_STATUS	RO	0x0	DAC synchronization status. Will be set to 1 while waiting for the external synchronization signal This bit has an effect only the EXT_SYNC synthesis parameter is set.
0x001C	0x0070	REG_DRP_CNTRL				DRP Control & Status
		[28]	DRP_RWN	RW	0x0	DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[27:16]	DRP_ADDRESS[11:0]	RW	0x00	DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[15:0]	RESERVED[15:0]	RO	0x0000	Reserved for backwards compatibility
0x001D	0x0074	REG_DRP_STATUS				DAC Interface Control & Status
		[17]	DRP_LOCKED	RO	0x0	If set indicates the MMCM/PLL is locked
		[16]	DRP_STATUS	RO	0x0	If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[15:0]	RESERVED[15:0]	RO	0x0000	Reserved for backwards compatibility
0x001E	0x0078	REG_DRP_WDATA				DAC Interface Control & Status
		[15:0]	DRP_WDATA[15:0]	RW	0x0000	DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x001F	0x007c	REG_DRP_RDATA				DAC Interface Control & Status
		[15:0]	DRP_RDATA	RO	0x0000	DRP read data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x0020	0x0080	REG_DAC_CUSTOM_RD				DAC Read Configuration Data
		[31:0]	DAC_CUSTOM_RD[31:0]	RO	0x00000000	Custom Read of the available registers.
0x0021	0x0084	REG_DAC_CUSTOM_WR				DAC Write Configuration Data
		[31:0]	DAC_CUSTOM_WR[31:0]	RW	0x00000000	Custom Write of the available registers.
0x0022	0x0088	REG_UI_STATUS				User Interface Status
		[4]	IF_BUSY	RO	0x0	Interface busy. If set, indicates that the data interface is busy.
		[1]	UI_OVF	RW1C	0x0	User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
		[0]	UI_UNF	RW1C	0x0	User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
0x0023	0x008c	REG_DAC_CUSTOM_CTRL				DAC Control Configuration Data
		[31:0]	DAC_CUSTOM_CTRL[31:0]	RW	0x00000000	Custom Control of the available registers.
0x0028	0x00a0	REG_USR_CNTRL_1				DAC User Control & Status
		[7:0]	USR_CHANMAX[7:0]	RW	0x00	This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x002E	0x00b8	REG_DAC_GPIO_IN				DAC GPIO inputs
		[31:0]	DAC_GPIO_IN[31:0]	RO	0x00000000	This reads auxiliary GPI pins of the DAC core
0x002F	0x00bc	REG_DAC_GPIO_OUT				DAC GPIO outputs
		[31:0]	DAC_GPIO_OUT[31:0]	RW	0x00000000	This controls auxiliary GPO pins of the DAC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).
Tue Mar 14 10:17:59 2023

DAC Channel (axi_ad*)

Click to expand regmap

0x0100	0x0400	REG_CHAN_CNTRL_1				DAC Channel Control & Status (channel - 0)
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[21:16]	DDS_PHASE_DW[5:0]	R	0x0000	The DDS phase data width offers the HDL parameter configuration with the same name. This information is used in conjunction with REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10. More info at https://wiki.analog.com/resources/fpga/docs/dds
		[15:0]	DDS_SCALE_1[15:0]	RW	0x0000	The DDS scale for tone 1. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0101	0x0404	REG_CHAN_CNTRL_2				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_INIT_1[15:0]	RW	0x0000	The DDS phase initialization for tone 1. Sets the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		[15:0]	DDS_INCR_1[15:0]	RW	0x0000	Sets the frequency of the phase accumulator. Its value can be calculated by ; where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase increment for tone 1 is extended in REG_CHAN_CNTRL_9. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0102	0x0408	REG_CHAN_CNTRL_3				DAC Channel Control & Status (channel - 0)
		[15:0]	DDS_SCALE_2[15:0]	RW	0x0000	The DDS scale for tone 2. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0103	0x040c	REG_CHAN_CNTRL_4				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_INIT_2[15:0]	RW	0x0000	The DDS phase initialization for tone 2. Sets the initial phase offset of the tone. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase init for tone 2 is extended in REG_CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		[15:0]	DDS_INCR_2[15:0]	RW	0x0000	Sets the frequency of the phase accumulator. Its value can be calculated by ; where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase increment for tone 2 is extended in REG_CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0104	0x0410	REG_CHAN_CNTRL_5				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_PATT_2[15:0]	RW	0x0000	The DDS data pattern for this channel.
		[15:0]	DDS_PATT_1[15:0]	RW	0x0000	The DDS data pattern for this channel.
0x0105	0x0414	REG_CHAN_CNTRL_6				DAC Channel Control & Status (channel - 0)
		[2]	IQCOR_ENB	RW	0x0	if set, enables IQ correction. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
		[1]	DAC_LB_OWR	RW	0x0	If set, forces DAC_DDS_SEL to 0x8, loopback If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
		[0]	DAC_PN_OWR	RW	0x0	IF set, forces DAC_DDS_SEL to 0x09, device specific pnX If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
0x0106	0x0418	REG_CHAN_CNTRL_7				DAC Channel Control & Status (channel - 0)
		[3:0]	DAC_DDS_SEL[3:0]	RW	0x00	Select internal data sources (available only if the DAC supports it). - 0x00: internal tone (DDS) - 0x01: pattern (SED) - 0x02: input data (DMA) - 0x03: 0x00 - 0x04: inverted pn7 - 0x05: inverted pn15 - 0x06: pn7 (standard O.150) - 0x07: pn15 (standard O.150) - 0x08: loopback data (ADC) - 0x09: pnX (Device specific e.g. ad9361) - 0x0A: Nibble ramp (Device specific e.g. adrv9001) - 0x0B: 16 bit ramp (Device specific e.g. adrv9001)
0x0107	0x041c	REG_CHAN_CNTRL_8				DAC Channel Control & Status (channel - 0)
		[31:16]	IQCOR_COEFF_1[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
		[15:0]	IQCOR_COEFF_2[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
0x0108	0x0420	REG_USR_CNTRL_3				DAC Channel Control & Status (channel - 0)
		[25]	USR_DATATYPE_BE	RW	0x0	The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[24]	USR_DATATYPE_SIGNED	RW	0x0	The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[23:16]	USR_DATATYPE_SHIFT[7:0]	RW	0x00	The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[15:8]	USR_DATATYPE_TOTAL_BITS[7:0]	RW	0x00	The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[7:0]	USR_DATATYPE_BITS[7:0]	RW	0x00	The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0109	0x0424	REG_USR_CNTRL_4				DAC Channel Control & Status (channel - 0)
		[31:16]	USR_INTERPOLATION_M[15:0]	RW	0x0000	This holds the user interpolation M value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[15:0]	USR_INTERPOLATION_N[15:0]	RW	0x0000	This holds the user interpolation N value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x010A	0x0428	REG_USR_CNTRL_5				DAC Channel Control & Status (channel - 0)
		[0]	DAC_IQ_MODE[0]	RW	0x0	Enable complex mode. In this mode the driven data to the DAC must be a sequence of I and Q sample pairs.
		[1]	DAC_IQ_SWAP[1]	RW	0x0	Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled.
0x010B	0x042c	REG_CHAN_CNTRL_9				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_INIT_1_EXTENDED[15:0]	RW	0x0000	The extended DDS phase initialization for tone 1. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from REG_CHAN_CNTRL_1 NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		[15:0]	DDS_INCR_1_EXTENDED[15:0]	RW	0x0000	Sets the frequency of tone 1's phase accumulator. Its value can be calculated by ; Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in REG_CHAN_CNTRL_1 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x010C	0x0430	REG_CHAN_CNTRL_10				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_INIT_2_EXTENDED[15:0]	RW	0x0000	The extended DDS phase initialization for tone 2. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from REG_CHAN_CNTRL_2 NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		[15:0]	DDS_INCR_2_EXTENDED[15:0]	RW	0x0000	Sets the frequency of tone 2's phase accumulator. Its value can be calculated by ; Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in REG_CHAN_CNTRL_2 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0110	0x0440	REG_*				Channel 1, similar to registers 0x100 to 0x10f.
0x0120	0x0480	REG_*				Channel 2, similar to registers 0x100 to 0x10f.
0x01F0	0x07c0	REG_*				Channel 15, similar to registers 0x100 to 0x10f.
Fri Sep 8 16:01:53 2023

Generic TDD Control (axi_tdd)

Click to expand regmap

0x0000	0x0000	VERSION				Version of the peripheral. Follows semantic versioning. Current version 2.00.61.
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:16]	VERSION_MAJOR	R	0x0002
		[15:8]	VERSION_MINOR	R	0x00
		[7:0]	VERSION_PATCH	R	0x61
0x0001	0x0004	PERIPHERAL_ID
		[31:0]	PERIPHERAL_ID	R	`ID`	Value of the ID configuration parameter.
0x0002	0x0008	SCRATCH
		[31:0]	SCRATCH	RW	0x00000000	Scratch register useful for debug.
0x0003	0x000c	IDENTIFICATION
		[31:0]	IDENTIFICATION	R	0x5444444E	Peripheral identification ('T', 'D', 'D', 'N').
0x0004	0x0010	INTERFACE_DESCRIPTION
		[30:24]	SYNC_COUNT_WIDTH	R	`SYNC_COUNT_WIDTH`	Width of internal synchronization counter
		[21:16]	BURST_COUNT_WIDTH	R	`BURST_COUNT_WIDTH`	Width of burst counter
		[13:8]	REGISTER_WIDTH	R	`REGISTER_WIDTH`	Width of internal reference counter and timing registers
		[7]	SYNC_EXTERNAL_CDC	R	`SYNC_EXTERNAL_CDC`	Enable CDC for external synchronization pulse
		[6]	SYNC_EXTERNAL	R	`SYNC_EXTERNAL`	Enable external synchronization support
		[5]	SYNC_INTERNAL	R	`SYNC_INTERNAL`	Enable internal synchronization support
		[4:0]	CHANNEL_COUNT_EXTRA	R	`CHANNEL_COUNT`-1	Number of channels starting from CH1, excluding CH0
0x0005	0x0014	DEFAULT_POLARITY
		[31:0]	DEFAULT_POLARITY	R	`DEFAULT_POLARITY`	Default polarity per every channel - LSB corresponds to CH0, MSB to CH31
0x0010	0x0040	CONTROL				TDD Control
		[4]	SYNC_SOFT	RW	0x0	Trigger the TDD core through a register write. This bit self clears.
		[3]	SYNC_EXT	RW	0x0	Enable external sync trigger. This bit is implemented if `SYNC_EXTERNAL` is set.
		[2]	SYNC_INT	RW	0x0	Enable internal sync trigger. This bit is implemented if `SYNC_INTERNAL` is set.
		[1]	SYNC_RST	RW	0x0	Reset the internal counter while running when receiving a sync event
		[0]	ENABLE	RW	0x0	Module enable
0x0011	0x0044	CHANNEL_ENABLE				TDD Channel Enable
		[31:0]	CHANNEL_ENABLE	RW	0x00000000	Enable bits per channel - LSB corresponds to CH0, MSB to CH31
0x0012	0x0048	CHANNEL_POLARITY				TDD Channel Polarity
		[31:0]	CHANNEL_POLARITY	RW	0x00000000	Polarity bits per channel - LSB corresponds to CH0, MSB to CH31
0x0013	0x004c	BURST_COUNT				TDD Number of frames per burst
		[31:0]	BURST_COUNT	RW	0x00000000	If set to 0x0 and enabled - the controller operates in TDD mode as long as the ENABLE bit is set. If set to a non-zero value, the controller operates for the set number of frames and then stops.
0x0014	0x0050	STARTUP_DELAY				TDD Transmission startup delay
		[31:0]	STARTUP_DELAY	RW	0x00000000	The initial delay value before the beginning of the first frame; defined in clock cycles.
0x0015	0x0054	FRAME_LENGTH				TDD Frame length
		[31:0]	FRAME_LENGTH	RW	0x00000000	The length of the transmission frame; defined in clock cycles.
0x0016	0x0058	SYNC_COUNTER_LOW				TDD Sync counter
		[31:0]	SYNC_COUNTER_LOW	RW	0x00000000	The LSB slice of the offset (from sync counter equal zero) when an internal sync pulse is generated. This register is implemented if `SYNC_COUNT_WIDTH`>0.
0x0017	0x005c	SYNC_COUNTER_HIGH				TDD Sync counter
		[31:0]	SYNC_COUNTER_HIGH	RW	0x00000000	The MSB slice of the offset (from sync counter equal zero) when an internal sync pulse is generated. This register is implemented if `SYNC_COUNT_WIDTH`>32.
0x0018	0x0060	STATUS				Peripheral Status
		[1:0]	STATE	R	0x0	The current state of the peripheral FSM; used for debugging purposes.
0x0020	0x0080	CH0_ON				Channel Set
		[31:0]	CH0_ON	RW	0x00000000	The offset (from frame count equal zero), when CH0 is set.
0x0021	0x0084	CH0_OFF				Channel Reset
		[31:0]	CH0_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH0 is reset.
0x0022	0x0088	CH1_ON				Channel Set
		[31:0]	CH1_ON	RW	0x00000000	The offset (from frame count equal zero), when CH1 is set. This register is implemented if `CHANNEL_COUNT`>1.
0x0023	0x008c	CH1_OFF				Channel Reset
		[31:0]	CH1_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH1 is reset. This register is implemented if `CHANNEL_COUNT`>1.
0x0024	0x0090	CH2_ON				Channel Set
		[31:0]	CH2_ON	RW	0x00000000	The offset (from frame count equal zero), when CH2 is set. This register is implemented if `CHANNEL_COUNT`>2.
0x0025	0x0094	CH2_OFF				Channel Reset
		[31:0]	CH2_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH2 is reset. This register is implemented if `CHANNEL_COUNT`>2.
0x0026	0x0098	CH3_ON				Channel Set
		[31:0]	CH3_ON	RW	0x00000000	The offset (from frame count equal zero), when CH3 is set. This register is implemented if `CHANNEL_COUNT`>3.
0x0027	0x009c	CH3_OFF				Channel Reset
		[31:0]	CH3_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH3 is reset. This register is implemented if `CHANNEL_COUNT`>3.
0x0028	0x00a0	CH4_ON				Channel Set
		[31:0]	CH4_ON	RW	0x00000000	The offset (from frame count equal zero), when CH4 is set. This register is implemented if `CHANNEL_COUNT`>4.
0x0029	0x00a4	CH4_OFF				Channel Reset
		[31:0]	CH4_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH4 is reset. This register is implemented if `CHANNEL_COUNT`>4.
0x002A	0x00a8	CH5_ON				Channel Set
		[31:0]	CH5_ON	RW	0x00000000	The offset (from frame count equal zero), when CH5 is set. This register is implemented if `CHANNEL_COUNT`>5.
0x002B	0x00ac	CH5_OFF				Channel Reset
		[31:0]	CH5_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH5 is reset. This register is implemented if `CHANNEL_COUNT`>5.
0x002C	0x00b0	CH6_ON				Channel Set
		[31:0]	CH6_ON	RW	0x00000000	The offset (from frame count equal zero), when CH6 is set. This register is implemented if `CHANNEL_COUNT`>6.
0x002D	0x00b4	CH6_OFF				Channel Reset
		[31:0]	CH6_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH6 is reset. This register is implemented if `CHANNEL_COUNT`>6.
0x002E	0x00b8	CH7_ON				Channel Set
		[31:0]	CH7_ON	RW	0x00000000	The offset (from frame count equal zero), when CH7 is set. This register is implemented if `CHANNEL_COUNT`>7.
0x002F	0x00bc	CH7_OFF				Channel Reset
		[31:0]	CH7_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH7 is reset. This register is implemented if `CHANNEL_COUNT`>7.
0x0030	0x00c0	CH8_ON				Channel Set
		[31:0]	CH8_ON	RW	0x00000000	The offset (from frame count equal zero), when CH8 is set. This register is implemented if `CHANNEL_COUNT`>8.
0x0031	0x00c4	CH8_OFF				Channel Reset
		[31:0]	CH8_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH8 is reset. This register is implemented if `CHANNEL_COUNT`>8.
0x0032	0x00c8	CH9_ON				Channel Set
		[31:0]	CH9_ON	RW	0x00000000	The offset (from frame count equal zero), when CH9 is set. This register is implemented if `CHANNEL_COUNT`>9.
0x0033	0x00cc	CH9_OFF				Channel Reset
		[31:0]	CH9_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH9 is reset. This register is implemented if `CHANNEL_COUNT`>9.
0x0034	0x00d0	CH10_ON				Channel Set
		[31:0]	CH10_ON	RW	0x00000000	The offset (from frame count equal zero), when CH10 is set. This register is implemented if `CHANNEL_COUNT`>10.
0x0035	0x00d4	CH10_OFF				Channel Reset
		[31:0]	CH10_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH10 is reset. This register is implemented if `CHANNEL_COUNT`>10.
0x0036	0x00d8	CH11_ON				Channel Set
		[31:0]	CH11_ON	RW	0x00000000	The offset (from frame count equal zero), when CH11 is set. This register is implemented if `CHANNEL_COUNT`>11.
0x0037	0x00dc	CH11_OFF				Channel Reset
		[31:0]	CH11_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH11 is reset. This register is implemented if `CHANNEL_COUNT`>11.
0x0038	0x00e0	CH12_ON				Channel Set
		[31:0]	CH12_ON	RW	0x00000000	The offset (from frame count equal zero), when CH12 is set. This register is implemented if `CHANNEL_COUNT`>12.
0x0039	0x00e4	CH12_OFF				Channel Reset
		[31:0]	CH12_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH12 is reset. This register is implemented if `CHANNEL_COUNT`>12.
0x003A	0x00e8	CH13_ON				Channel Set
		[31:0]	CH13_ON	RW	0x00000000	The offset (from frame count equal zero), when CH13 is set. This register is implemented if `CHANNEL_COUNT`>13.
0x003B	0x00ec	CH13_OFF				Channel Reset
		[31:0]	CH13_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH13 is reset. This register is implemented if `CHANNEL_COUNT`>13.
0x003C	0x00f0	CH14_ON				Channel Set
		[31:0]	CH14_ON	RW	0x00000000	The offset (from frame count equal zero), when CH14 is set. This register is implemented if `CHANNEL_COUNT`>14.
0x003D	0x00f4	CH14_OFF				Channel Reset
		[31:0]	CH14_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH14 is reset. This register is implemented if `CHANNEL_COUNT`>14.
0x003E	0x00f8	CH15_ON				Channel Set
		[31:0]	CH15_ON	RW	0x00000000	The offset (from frame count equal zero), when CH15 is set. This register is implemented if `CHANNEL_COUNT`>15.
0x003F	0x00fc	CH15_OFF				Channel Reset
		[31:0]	CH15_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH15 is reset. This register is implemented if `CHANNEL_COUNT`>15.
0x0040	0x0100	CH16_ON				Channel Set
		[31:0]	CH16_ON	RW	0x00000000	The offset (from frame count equal zero), when CH16 is set. This register is implemented if `CHANNEL_COUNT`>16.
0x0041	0x0104	CH16_OFF				Channel Reset
		[31:0]	CH16_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH16 is reset. This register is implemented if `CHANNEL_COUNT`>16.
0x0042	0x0108	CH17_ON				Channel Set
		[31:0]	CH17_ON	RW	0x00000000	The offset (from frame count equal zero), when CH17 is set. This register is implemented if `CHANNEL_COUNT`>17.
0x0043	0x010c	CH17_OFF				Channel Reset
		[31:0]	CH17_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH17 is reset. This register is implemented if `CHANNEL_COUNT`>17.
0x0044	0x0110	CH18_ON				Channel Set
		[31:0]	CH18_ON	RW	0x00000000	The offset (from frame count equal zero), when CH18 is set. This register is implemented if `CHANNEL_COUNT`>18.
0x0045	0x0114	CH18_OFF				Channel Reset
		[31:0]	CH18_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH18 is reset. This register is implemented if `CHANNEL_COUNT`>18.
0x0046	0x0118	CH19_ON				Channel Set
		[31:0]	CH19_ON	RW	0x00000000	The offset (from frame count equal zero), when CH19 is set. This register is implemented if `CHANNEL_COUNT`>19.
0x0047	0x011c	CH19_OFF				Channel Reset
		[31:0]	CH19_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH19 is reset. This register is implemented if `CHANNEL_COUNT`>19.
0x0048	0x0120	CH20_ON				Channel Set
		[31:0]	CH20_ON	RW	0x00000000	The offset (from frame count equal zero), when CH20 is set. This register is implemented if `CHANNEL_COUNT`>20.
0x0049	0x0124	CH20_OFF				Channel Reset
		[31:0]	CH20_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH20 is reset. This register is implemented if `CHANNEL_COUNT`>20.
0x004A	0x0128	CH21_ON				Channel Set
		[31:0]	CH21_ON	RW	0x00000000	The offset (from frame count equal zero), when CH21 is set. This register is implemented if `CHANNEL_COUNT`>21.
0x004B	0x012c	CH21_OFF				Channel Reset
		[31:0]	CH21_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH21 is reset. This register is implemented if `CHANNEL_COUNT`>21.
0x004C	0x0130	CH22_ON				Channel Set
		[31:0]	CH22_ON	RW	0x00000000	The offset (from frame count equal zero), when CH22 is set. This register is implemented if `CHANNEL_COUNT`>22.
0x004D	0x0134	CH22_OFF				Channel Reset
		[31:0]	CH22_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH22 is reset. This register is implemented if `CHANNEL_COUNT`>22.
0x004E	0x0138	CH23_ON				Channel Set
		[31:0]	CH23_ON	RW	0x00000000	The offset (from frame count equal zero), when CH23 is set. This register is implemented if `CHANNEL_COUNT`>23.
0x004F	0x013c	CH23_OFF				Channel Reset
		[31:0]	CH23_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH23 is reset. This register is implemented if `CHANNEL_COUNT`>23.
0x0050	0x0140	CH24_ON				Channel Set
		[31:0]	CH24_ON	RW	0x00000000	The offset (from frame count equal zero), when CH24 is set. This register is implemented if `CHANNEL_COUNT`>24.
0x0051	0x0144	CH24_OFF				Channel Reset
		[31:0]	CH24_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH24 is reset. This register is implemented if `CHANNEL_COUNT`>24.
0x0052	0x0148	CH25_ON				Channel Set
		[31:0]	CH25_ON	RW	0x00000000	The offset (from frame count equal zero), when CH25 is set. This register is implemented if `CHANNEL_COUNT`>25.
0x0053	0x014c	CH25_OFF				Channel Reset
		[31:0]	CH25_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH25 is reset. This register is implemented if `CHANNEL_COUNT`>25.
0x0054	0x0150	CH26_ON				Channel Set
		[31:0]	CH26_ON	RW	0x00000000	The offset (from frame count equal zero), when CH26 is set. This register is implemented if `CHANNEL_COUNT`>26.
0x0055	0x0154	CH26_OFF				Channel Reset
		[31:0]	CH26_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH26 is reset. This register is implemented if `CHANNEL_COUNT`>26.
0x0056	0x0158	CH27_ON				Channel Set
		[31:0]	CH27_ON	RW	0x00000000	The offset (from frame count equal zero), when CH27 is set. This register is implemented if `CHANNEL_COUNT`>27.
0x0057	0x015c	CH27_OFF				Channel Reset
		[31:0]	CH27_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH27 is reset. This register is implemented if `CHANNEL_COUNT`>27.
0x0058	0x0160	CH28_ON				Channel Set
		[31:0]	CH28_ON	RW	0x00000000	The offset (from frame count equal zero), when CH28 is set. This register is implemented if `CHANNEL_COUNT`>28.
0x0059	0x0164	CH28_OFF				Channel Reset
		[31:0]	CH28_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH28 is reset. This register is implemented if `CHANNEL_COUNT`>28.
0x005A	0x0168	CH29_ON				Channel Set
		[31:0]	CH29_ON	RW	0x00000000	The offset (from frame count equal zero), when CH29 is set. This register is implemented if `CHANNEL_COUNT`>29.
0x005B	0x016c	CH29_OFF				Channel Reset
		[31:0]	CH29_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH29 is reset. This register is implemented if `CHANNEL_COUNT`>29.
0x005C	0x0170	CH30_ON				Channel Set
		[31:0]	CH30_ON	RW	0x00000000	The offset (from frame count equal zero), when CH30 is set. This register is implemented if `CHANNEL_COUNT`>30.
0x005D	0x0174	CH30_OFF				Channel Reset
		[31:0]	CH30_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH30 is reset. This register is implemented if `CHANNEL_COUNT`>30.
0x005E	0x0178	CH31_ON				Channel Set
		[31:0]	CH31_ON	RW	0x00000000	The offset (from frame count equal zero), when CH31 is set. This register is implemented if `CHANNEL_COUNT`>31.
0x005F	0x017c	CH31_OFF				Channel Reset
		[31:0]	CH31_OFF	RW	0x00000000	The offset (from frame count equal zero), when CH31 is reset. This register is implemented if `CHANNEL_COUNT`>31.
Tue Mar 14 10:17:59 2023

Transceiver TDD Control (axi_ad*)

Click to expand regmap

0x0010	0x0040	REG_TDD_CONTROL_0				TDD Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[5]	TDD_GATED_TX_DMAPATH	RW	0x0	If this bit is set, the core requests data from the TX DMA, just when the data path is active. Otherwise will requests continuously on the adjusted rate. The purpose of this feature is to facilitate debug. This bit must be SET to preserve data integrity.
		[4]	TDD_GATED_RX_DMAPATH	RW	0x0	If this bit is set, the core provides data for the RX DMA, just when the data path is active. Otherwise will provides continuously on the adjusted rate. The purpose of this feature is to facilitate debug. This bit must be SET to preserve data integrity.
		[3]	TDD_TXONLY	RW	0x0	If this bit is set- the TDD controller ignores all the TX_* timing registers below and assumes continuous receive operation within a frame.
		[2]	TDD_RXONLY	RW	0x0	If this bit is set- the TDD controller ignores all the RX_* timing registers below and assumes continuous transmit operation within a frame.
		[1]	TDD_SECONDARY	RW	0x0	Enable the secondary transmit/receive on the active frame. If this bit is clear the controller only uses the _1 timing registers below. If this bit is set - the controller uses the _1 and _2 timing registers below.
		[0]	TDD_ENABLE	RW	0x0	If set, enables the TDD controller- software must set this bit after programming all the registers that controls the tdd timing. Any device settings needs to be done (for example bring the AD9361 to the alert state) prior to to setting this bit. The controller keeps the frame counters in reset if this bit is reset. A 0 to 1 transition in this bit starts the frame counter and tdd mode of operation.
0x0011	0x0044	REG_TDD_CONTROL_1				TDD Control & Status
		[7:0]	TDD_BURST_COUNT	RW	0x00	If set to 0x0 and enabled (TDD_ENABLE is set) - the controller operates in TDD mode as long as the TDD_ENABLE bit is set. If set to a non-zero value, the controller operates for the set number of frames and stops.
0x0012	0x0048	REG_TDD_CONTROL_2				TDD Control & Status
		[23:0]	TDD_COUNTER_INIT	RW	0x000000	The controller sets the frame counter to this value when starting TDD operation. This is the starting offset value for the TDD frame counter.
0x0013	0x004c	REG_TDD_FRAME_LENGTH				TDD Control & Status
		[23:0]	TDD_FRAME_LENGTH	RW	0x000000	The frame length is the terminal count for the 10ms counter running at the digital interface clock- as an example for a 245.76MHz clock it is 0x258000.
0x0014	0x0050	REG_TDD_SYNC_TERMINAL_TYPE				TDD Control & Status
		[0]	TDD_SYNC_TERMINAL_TYPE	RW	0x0	Set this bit, if the current terminal will generate the syncronization pulse, reset otherwise.
0x0018	0x0060	REG_TDD_STATUS				TDD Control & Status
		[0]	TDD_RXTX_VCO_OVERLAP	RO	0x0	This bit is asserted, if exist a time interval when both the TX and RX VCOs are powered up.
		[1]	TDD_RXTX_RF_OVERLAP	RO	0x0	This bit is asserted, if exist a time interval when both the TX and RX RF datapath are powered up.
0x0020	0x0080	REG_TDD_VCO_RX_ON_1				TDD Control & Status
		[23:0]	TDD_VCO_RX_ON_1	RW	0x000000	Defines the offset (from frame count equal zero), when the RX VCO powers up at the first time. The controller enables the receive VCO, when the frame count reaches this value. The VCO may have to be enabled before data can be received. The user needs to make sure, that the RF device is in a state, from where this operation is valid.
0x0021	0x0084	REG_TDD_VCO_RX_OFF_1				TDD Control & Status
		[23:0]	TDD_VCO_RX_OFF_1	RW	0x000000	Defines the offset (from frame count equal zero), when the RX VCO powers down at the first time. The controller disables the receive VCO, when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.
0x0022	0x0088	REG_TDD_VCO_TX_ON_1				TDD Control & Status
		[23:0]	TDD_VCO_TX_ON_1	RW	0x000000	Defines the offset (from frame count equal zero), when the TX VCO powers up at the first time. The controller enables the transmit VCO, when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.
0x0023	0x008c	REG_TDD_VCO_TX_OFF_1				TDD Control & Status
		[23:0]	TDD_VCO_TX_OFF_1	RW	0x000000	Defines the offset (from frame count equal zero), when the TX VCO powers down at the first time. The controller disables the transmit VCO when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.
0x0024	0x0090	REG_TDD_RX_ON_1				TDD Control & Status
		[23:0]	TDD_RX_ON_1	RW	0x000000	Defines the offset (from frame count equal zero), when the RX data path is activated at the first time. The controller enables the receive chain when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.
0x0025	0x0094	REG_TDD_RX_OFF_1				TDD Control & Status
		[23:0]	TDD_RX_OFF_1	RW	0x000000	Defines the offset (from frame count equal zero), when the RX data path is deactivated the first time. The controller disables the receive chain when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.
0x0026	0x0098	REG_TDD_TX_ON_1				TDD Control & Status
		[23:0]	TDD_TX_ON_1	RW	0x000000	Defines the offset (from frame count equal zero), when the TX data path is activated at the first time. The controller enables the transmit chain, when the frame count reaches this value. This register and the TX_DP_ON register controls the delay between the data path being activated and the time to actually push the transmit data through the transmit chain in the device.
0x0027	0x009c	REG_TDD_TX_OFF_1				TDD Control & Status
		[23:0]	TDD_TX_OFF_1	RW	0x000000	Defines the offset (from frame count equal zero), when the TX data path is deactivated at the first time. The controller disables the transmit chain, when the frame count reaches this value. This register and the TX_DP_OFF register controls the delay between the data path being deactivated and the time to actually stop transmitting data through the transmit chain in the device.
0x0028	0x00a0	REG_TDD_RX_DP_ON_1				TDD Control & Status
		[23:0]	TDD_RX_DP_ON_1	RW	0x000000	Defines the offset (from frame count equal zero), when the controller starts to accept data from the digital interface for receive.
0x0029	0x00a4	REG_TDD_RX_DP_OFF_1				TDD Control & Status
		[23:0]	TDD_RX_DP_OFF_1	RW	0x000000	Defines the offset (from frame count equal zero), when the controller stops to accept data from the digital interface for receive.
0x002A	0x00a8	REG_TDD_TX_DP_ON_1				TDD Control & Status
		[23:0]	TDD_TX_DP_ON_1	RW	0x000000	Defines the offset (from frame count equal zero), when the controller starts to request data from the system memory for transmit. The data rate is controlled by the TDD controller.
0x002B	0x00ac	REG_TDD_TX_DP_OFF_1				TDD Control & Status
		[23:0]	TDD_TX_DP_OFF_1	RW	0x000000	Defines the offset (from frame count equal zero), when the controller stop requesting data from the system memory for transmit.
0x0030	0x00c0	REG_TDD_VCO_RX_ON_2				TDD Control & Status
		[23:0]	TDD_VCO_RX_ON_2	RW	0x000000	The secondary pointer for VCO_RX_ON.
0x0031	0x00c4	REG_TDD_VCO_RX_OFF_2				TDD Control & Status
		[23:0]	TDD_VCO_RX_OFF_2	RW	0x000000	The secondary pointer for VCO_RX_OFF.
0x0032	0x00c8	REG_TDD_VCO_TX_ON_2				TDD Control & Status
		[23:0]	TDD_VCO_TX_ON_2	RW	0x000000	The secondary pointer for VCO_TX_ON.
0x0033	0x00cc	REG_TDD_VCO_TX_OFF_2				TDD Control & Status
		[23:0]	TDD_VCO_TX_OFF_2	RW	0x000000	The secondary pointer for VCO_TX_OFF.
0x0034	0x00d0	REG_TDD_RX_ON_2				TDD Control & Status
		[23:0]	TDD_RX_ON_2	RW	0x000000	The secondary pointer for RX_ON.
0x0035	0x00d4	REG_TDD_RX_OFF_2				TDD Control & Status
		[23:0]	TDD_RX_OFF_2	RW	0x000000	The secondary pointer for RX_OFF.
0x0036	0x00d8	REG_TDD_TX_ON_2				TDD Control & Status
		[23:0]	TDD_TX_ON_2	RW	0x000000	The secondary pointer for TX_ON.
0x0037	0x00dc	REG_TDD_TX_OFF_2				TDD Control & Status
		[23:0]	TDD_TX_OFF_2	RW	0x000000	The secondary pointer for TX_OFF.
0x0038	0x00e0	REG_TDD_RX_DP_ON_2				TDD Control & Status
		[23:0]	TDD_RX_DP_ON_2	RW	0x000000	The secondary pointer for RX_DP_ON.
0x0039	0x00e4	REG_TDD_RX_DP_OFF_2				TDD Control & Status
		[23:0]	TDD_RX_DP_OFF_2	RW	0x000000	The secondary pointer for RX_DP_OFF.
0x003A	0x00e8	REG_TDD_TX_DP_ON_2				TDD Control & Status
		[23:0]	TDD_TX_DP_ON_2	RW	0x000000	The secondary pointer for TX_DP_ON.
0x003B	0x00ec	REG_TDD_TX_DP_OFF_2				TDD Control & Status
		[23:0]	TDD_TX_DP_OFF_2	RW	0x000000	The secondary pointer for TX_DP_OFF.
Tue Mar 14 10:17:59 2023

JESD TPL (up_tpl_common)

Click to expand regmap

0x00080	0x0200	REG_TPL_CNTRL				JESD, TPL Control
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[3:0]	PROFILE_SEL	RW	0x00	Selects one of the available deframer/framers from the transport layer. Valid only if `PROFILE_NUM` > 1.
0x00081	0x0204	REG_TPL_STATUS				JESD, TPL Status
		[3:0]	PROFILE_NUM	RO	0x00	Number of supported framer/deframer profiles.
0x00090	0x0240	REG_TPL_DESCRIPTOR_1				JESD, TPL descriptor for profile
		[31:24]	JESD_F	RO	0x00	Octets per Frame per Lane.
		[23:16]	JESD_S	RO	0x00	Samples per Converter per Frame.
		[15:8]	JESD_L	RO	0x00	Lane Count.
		[7:0]	JESD_M	RO	0x00	Converter Count.
0x00091	0x0244	REG_TPL_DESCRIPTOR_2				JESD, TPL descriptor for profile
		[7:0]	JESD_N	RO	0x00	Converter Resolution.
		[15:8]	JESD_NP	RO	0x00	Total Number of Bits per Sample.
0x00092	0x0248	REG_*				Profile 1, similar to registers 0x00010 to 0x00011.
0x00094	0x0250	REG_*				Profile 2, similar to registers 0x00010 to 0x00011.
Tue Mar 14 10:17:59 2023

JESD204 RX (axi_jesd204_rx)

Click to expand regmap

0x00	0x0000	VERSION				Version of the peripheral. Follows semantic versioning. Current version 1.03.a.
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:16]	VERSION_MAJOR	RO	0x0001
		[15:8]	VERSION_MINOR	RO	0x03
		[7:0]	VERSION_PATCH	RO	0x61
0x01	0x0004	PERIPHERAL_ID
		[31:0]	PERIPHERAL_ID	RO	0x????????	Value of the ID configuration parameter.
0x02	0x0008	SCRATCH
		[31:0]	SCRATCH	RW	0x00000000	Scratch register useful for debug.
0x03	0x000c	IDENTIFICATION
		[31:0]	IDENTIFICATION	RO	0x32303452	Peripheral identification ('2', '0', '4', 'R').
0x04	0x0010	SYNTH_NUM_LANES
		[31:0]	SYNTH_NUM_LANES	RO	0x????????	Number of supported lanes.
0x05	0x0014	SYNTH_DATA_PATH_WIDTH
		[31:16]	Reserved	RO	0x0000
		[15:8]	TPL_DATA_PATH_WIDTH	RO	0x00000002	Data path width in octets at Transport Layer interface. Available starting from version 1.07.a;
		[7:0]	SYNTH_DATA_PATH_WIDTH	RO	0x00000002	Log2 of internal data path width in octets. Represents the datapath width towards the physical interface.
0x06	0x0018	SYNTH_REG_1				Core description register.
		[31:19]	Reserved	RO	0x0000
		[18]	ENABLE_CHAR_REPLACE	RO	0x00	This bit reflects the presence of character replacement monitoring logic for cases when scrambling is disabled. Available starting from version 1.07.a;
		[17]	ENABLE_FRAME_ALIGN_ERR_RESET	RO	0x00	If this bit is set in case of frame misalignment is detected the core resets itself. No software intervention is required. If the bit is not set and misalignment is detected the software must restart the link. Available starting from version 1.07.a;
		[16]	ENABLE_FRAME_ALIGN_CHECK	RO	0x00	This bit reflects the presence of frame alignment monitor. Available starting from version 1.07.a;
		[12]	ASYNC_CLK	RO	ASYNC_CLK	This bit is set if link clock and device clock are connected to different sources. This is useful for supporting modes where datapath width is not integer multiple of F. Available starting from version 1.07.a;
		[9:8]	DECODER	RO	0x??	Decoder presence: 01 - 8B10B decoder 10 - 64B66B decoder
		[7:0]	NUM_LINKS	RO	0x??	Maximum supported links. Valid for 8B/10B encoder.
0x10	0x0040	SYNTH_ELASTIC_BUFFER_SIZE
		[31:0]	SYNTH_ELASTIC_BUFFER_SIZE	RO	0x00000100	Elastic buffer size in octets.
0x20	0x0080	IRQ_ENABLE
		[31:0]	IRQ_ENABLE	RW	0x00000000	Interrupt enable.
0x21	0x0084	IRQ_PENDING
		[31:0]	IRQ_PENDING	RW1C-V	0x00000000	Pending and enabled interrupts.
0x22	0x0088	IRQ_SOURCE
		[31:0]	IRQ_SOURCE	RW1C-V	0x00000000	Pending interrupts.
0x30	0x00c0	LINK_DISABLE				JESD204B link disable.
		[31:1]	Reserved	RO	0x00
		[0]	LINK_DISABLE	RW	0x1	0 = Enable link, 1 = Disable link.
0x31	0x00c4	LINK_STATE				JESD204B link state.
		[31:2]	Reserved	RO	0x00
		[1]	EXTERNAL_RESET	RO	0x?	0 = External reset de-asserted, 1 = External reset asserted.
		[0]	LINK_STATE	RO	0x1	0 = Link enabled, 1 = Link disabled.
0x32	0x00c8	LINK_CLK_FREQ
		[20:0]	LINK_CLK_FREQ	RO-V	0x?????????	Ratio of the link_clk frequency relative to the s_axi_aclk. Format is 16.16.
0x33	0x00cc	DEVICE_CLK_FREQ
		[20:0]	DEVICE_CLK_FREQ	RO-V	0x?????????	Ratio of the device_clk frequency relative to the s_axi_aclk. Format is 16.16. Available starting from version 1.07.a;
0x40	0x0100	SYSREF_CONF				SYSREF configuration
		[31:2]	Reserved	RO	0x00
		[1]	SYSREF_ONESHOT	RW	0x0	In oneshot mode only the first occurrence of the SYSREF signal is used for alignment.
		[0]	SYSREF_DISABLE	RW	0x0	Enable/Disable SYSREF handling.
0x41	0x0104	SYSREF_LMFC_OFFSET				SYSREF LMFC offset
		[31:10]	Reserved	RO	0x00
		[9:0]	SYSREF_LMFC_OFFSET	RW	0x00	Offset between SYSREF event and internal LMFC event in octets.
0x42	0x0108	SYSREF_STATUS				SYSREF status
		[31:2]	Reserved	RO	0x00
		[1]	SYSREF_ALIGNMENT_ERROR	RW1C-V	0x0	Indicates that an external SYSREF event has been observed that was unaligned to a previously observed event.
		[0]	SYSREF_DETECTED	RW1C-V	0x0	Indicates that an external SYSREF event has been observed.
0x80	0x0200	LANES_DISABLE				Enabled/Disabled lanes.
		[n]	LANE_DISABLEn	RW	0x0	Enable/Disable n-th lane (0 = enabled, 1 = disabled).
0x84	0x0210	LINK_CONF0				JESD204B link configuration.
		[31:19]	Reserved	RO	0x00
		[18:16]	OCTETS_PER_FRAME	RW	0x00	Number of octets per frame - 1 (F).
		[15:10]	Reserved	RO	0x00
		[9:0]	OCTETS_PER_MULTIFRAME	RW	0x03	Number of octets per multi-frame - 1 (K x F). In 64B/66B mode represents the number of octets per extended multiblock.
0x85	0x0214	LINK_CONF1				JESD204B link configuration.
		[31:2]	Reserved	RO	0x0
		[1]	CHAR_REPLACEMENT_DISABLE	RW	0x0	Enable/Disable user data alignment character replacement (0 = enabled, 1 = disabled). Valid for 8B/10B encoder.
		[0]	DESCRAMBLER_DISABLE	RW	0x0	Enable/Disable user data descrambling (0 = enabled, 1 = disabled).
0x86	0x0218	MULTI_LINK_DISABLE				Enable/Disable links in case of a multi-link architecture. Valid for 8B/10B encoder.
		[n]	LINK_DISABLEn	RW	0x0	Enable/Disable n-th link (0 = enabled, 1 = disabled).
0x87	0x021c	LINK_CONF4				JESD204B link configuration.
		[31:8]	Reserved	RO	0x0
		[7:0]	TPL_BEATS_PER_MULTIFRAME	RW	0x00	Number of beats per multi-frame - 1 (K x F / TPL_DATA_PATH_WIDTH) at interface to Transport Layer. In 64B/66B mode represents the number of octets per extended multiblock. Available starting from version 1.07.a;
0x90	0x0240	LINK_CONF2				JESD204B link configuration.
		[31:17]	Reserved	RO	0x0
		[16]	BUFFER_EARLY_RELEASE	RW	0x0	Elastic buffer release point.
		[15:10]	Reserved	RO	0x0
		[9:0]	BUFFER_DEALY	RW	0x0	Buffer release opportunity offset from LMFC.
0x91	0x0244	LINK_CONF3				JESD204B error statistics configuration.
		[31:15]	Reserved	RO	0x0
		[14]	MASK_INVALID_HEADER	RW	0x0	If set, invalid header errors are not counted; Valid for 64B/66B encoder.
		[13]	MASK_UNEXPECTED_EOMB	RW	0x0	If set, unexpected end of multiblock errors are not counted; Valid for 64B/66B encoder.
		[12]	MASK_UNEXPECTED_EOEMB	RW	0x0	If set, unexpected end of extended multiblock errors are not counted; Valid for 64B/66B encoder.
		[11]	MASK_CRC_MISMATCH	RW	0x0	If set, CRC mismatch errors are not counted. Valid for 64B/66B encoder.
		[10]	MASK_UNEXPECTEDK	RW	0x0	If set, unexpected k errors are not counted. Valid for 8B/10B encoder.
		[9]	MASK_NOTINTABLE	RW	0x0	If set, not in table errors are not counted. Valid for 8B/10B encoder.
		[8]	MASK_DISPERR	RW	0x0	If set, disparity errors are not counted. Valid for 8B/10B encoder.
		[7:1]	Reserved	RO	0x0
		[0]	RESET_COUNTER	RW	0x0	If set, resets the error counter
0xa0	0x0280	LINK_STATUS				JESD204B link status.
		[31:2]	Reserved	RO	0x00
		[1:0]	STATUS_STATE	RO-V	0x00	8B/10B : State of the 8B/10B link state machine. (0 = RESET, 1 = WAIT_FOR_PHY, 2 = CGS, 3 = SYNCHRONIZED) 64B/66B : State of the 64B/66B link state machine. (0 = RESET, 1 = WAIT_BS, 2 = BLOCK_SYNC, 3 = DATA)
0xc0 + 0x08*n	0x0300 +0x20*n	LANEn_STATUS
		[31:11]	Reserved	RO	0x0
		[10:8]	EMB_STATE	RO	0x0	State of Extended multiblock alignment: 001 - EMB_INIT 010 - EMB_HUNT 100 - EMB_LOCK Valid for 64b66b encoder.
		[7:6]	Reserved	RO	0x0
		[5]	ILAS_READY	RO-V	0x0	ILAS configuration data received.
		[4]	IFS_READY	RO-V	0x0	Frame synchronization state.
		[3:2]	Reserved	RO	0x0
		[1:0]	CGS_STATE	RO-V	0x0	State of the lane code group synchronization. (0 = INIT, 1 = CHECK, 2 = DATA)
0xc1 + 0x08*n	0x0304 +0x20*n	LANEn_LATENCY
		[31:14]	Reserved	RO	0x0
		[13:0]	LATENCY	RO-V	0x0	For 8b10b mode: represents the lane latency in octets; For 64b66b mode: represents the delay from the received EOEMB indicator to the next (SYSREF aligned) LEMC edge in octets. In other words, this amount of data is stored in the elastic buffer before it gets released on the LEMC edge. Must be greater than 64. Its max value is KxF octets. Where LEMC period = KxF/8 link clock periods.
0xc2 + 0x08*n	0x0308 +0x20*n	LANEn_ERROR_STATISTICS
		[31:0]	ERROR_REGISTER	RO	0x0	This register shows the number of total errors for this lane. Errors counted depend on the configuration in LINK_CONF3. It must always be manually reset.
0xc3 + 0x08*n	0x030c +0x20*n	LANEn_LANE_FRAME_ALIGN_ERR_CNT
		[7:0]	ERROR_REGISTER	RO	0x0	This register shows the number of frame alignment errors for this lane. It resets with a link restart.
0xc4 + 0x08*n	0x0310 +0x20*n	LANEn_ILAS0				Received ILAS config data for the n-th lane.
		[31:28]	Reserved	RO	0x0
		[27:24]	BID	RO	0x0	BID (Bank ID) field of the ILAS config sequence.
		[23:16]	DID	RO	0x00	DID (Device ID) field of the ILAS config sequence.
		[15:0]	Reserved	RO	0x0000
0xc5 + 0x08*n	0x0314 +0x20*n	LANEn_ILAS1				Received ILAS config data for the n-th lane.
		[31:29]	Reserved	RO	0x00
		[28:24]	K	RO	0x00	K (Frames per multi-frame) field of the ILAS config sequence - 1.
		[23:16]	F	RO	0x00	F (Octets per frame) field of the ILAS config sequence - 1.
		[15]	SCR	RO	0x0	SCR (Scrambling enabled) field of the ILAS config sequence.
		[14:13]	Reserved	RO	0x0
		[12:8]	L	RO	0x00	L (Number of lanes) field of the ILAS config sequence - 1.
		[7:5]	Reserved	RO	0x0
		[4:0]	LID	RO	0x00	LID (Lane ID) field of the ILAS config sequence.
0xc6 + 0x08*n	0x0318 +0x20*n	LANEn_ILAS2				Received ILAS config data for the n-th lane.
		[31:29]	JESDV	RO	0x0	JESDV (JESD204 version) field of the ILAS config sequence.
		[28:24]	S	RO	0x00	S (Samples per frame) field of the ILAS config sequence - 1.
		[23:21]	SUBCLASSV	RO	0x0	SUBCLASSV (JESD204B subclass) field of the ILAS config sequence.
		[20:16]	NP	RO	0x00	N' (Total number of bits per sample) field of the ILAS config sequence - 1.
		[15:14]	CS	RO	0x0	CS (Control bits per sample) field of the ILAS config sequence.
		[13]	Reserved	RO	0x0
		[12:8]	N	RO	0x00	N (Converter resolution) field of the ILAS config sequence - 1.
		[7:0]	M	RO	0x00	M (Number of converters) field of the ILAS config sequence - 1.
0xc7 + 0x08*n	0x031c +0x20*n	LANEn_ILAS3				Received ILAS config data for the n-th lane.
		[31:24]	FCHK	RO	0x00	FCHK (Checksum) field of the ILAS config sequence.
		[23:8]	Reserved	RO	0x0
		[7]	HD	RO	0x0	HD (High-density) field of the ILAS config sequence.
		[6:5]	Reserved	RO	0x0
		[4:0]	CF	RO	0x00	CF (control words per frame) field of the ILAS config sequence
Tue Mar 14 10:17:59 2023

JESD204 TX (axi_jesd204_tx)

Click to expand regmap

0x00	0x0000	VERSION				Version of the peripheral. Follows semantic versioning. Current version 1.03.a.
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:16]	VERSION_MAJOR	RO	0x0001
		[15:8]	VERSION_MINOR	RO	0x03
		[7:0]	VERSION_PATCH	RO	0x61
0x01	0x0004	PERIPHERAL_ID
		[31:0]	PERIPHERAL_ID	RO	0x????????	Value of the ID configuration parameter.
0x02	0x0008	SCRATCH
		[31:0]	SCRATCH	RW	0x00000000	Scratch register useful for debug.
0x03	0x000c	IDENTIFICATION
		[31:0]	IDENTIFICATION	RO	0x32303454	Peripheral identification ('2', '0', '4', 'T').
0x04	0x0010	SYNTH_NUM_LANES
		[31:0]	SYNTH_NUM_LANES	RO	0x????????	Number of supported lanes.
0x05	0x0014	SYNTH_DATA_PATH_WIDTH
		[31:16]	Reserved	RO	0x0000
		[15:8]	TPL_DATA_PATH_WIDTH	RO	0x00000002	Data path width in octets at Transport Layer interface. Available starting from version 1.06.a;
		[7:0]	SYNTH_DATA_PATH_WIDTH	RO	0x00000002	Log2 of internal data path width in octets. Represents the datapath width towards the physical interface.
0x06	0x0018	SYNTH_REG_1				Core description register.
		[31:19]	Reserved	RO	0x0000
		[18]	ENABLE_CHAR_REPLACE	RO	0x00	This bit reflects the presence of character replacement insertion logic for cases when scrambling is disabled. Available starting from version 1.06.a;
		[12]	ASYNC_CLK	RO	ASYNC_CLK	This bit is set if link clock and device clock are connected to different sources. This is useful for supporting modes where datapath width is not integer multiple of F. Available starting from version 1.06.a;
		[9:8]	ENCODER	RO	0x??	Encoder presence: 01 - 8B10B encoder 10 - 64B66B encoder
		[7:0]	NUM_LINKS	RO	0x??	Maximum supported links. Valid for 8B/10B link.
0x20	0x0080	IRQ_ENABLE
		[31:0]	IRQ_ENABLE	RW	0x00000000	Interrupt enable.
0x21	0x0084	IRQ_PENDING
		[31:0]	IRQ_PENDING	RW1C-V	0x00000000	Pending and enabled interrupts.
0x22	0x0088	IRQ_SOURCE
		[31:0]	IRQ_SOURCE	RW1C-V	0x00000000	Pending interrupts.
0x30	0x00c0	LINK_DISABLE				JESD204B link disable.
		[31:1]	Reserved	RO	0x00
		[0]	LINK_DISABLE	RW	0x1	0 = Enable link, 1 = Disable link.
0x31	0x00c4	LINK_STATE				JESD204B link state.
		[31:2]	Reserved	RO	0x00
		[1]	EXTERNAL_RESET	RO	0x?	0 = External reset de-asserted, 1 = External reset asserted.
		[0]	LINK_STATE	RO	0x1	0 = Link enabled, 1 = Link disabled.
0x32	0x00c8	LINK_CLK_FREQ
		[31:0]	LINK_CLK_FREQ	RO-V	0x?????????	Ratio of the link_clk frequency relative to the s_axi_aclk. Format is 16.16.
0x33	0x00cc	DEVICE_CLK_FREQ
		[20:0]	DEVICE_CLK_FREQ	RO-V	0x?????????	Ratio of the device_clk frequency relative to the s_axi_aclk. Format is 16.16. Available starting from version 1.06.a;
0x40	0x0100	SYSREF_CONF				SYSREF configuration
		[31:2]	Reserved	RO	0x00
		[1]	SYSREF_ONESHOT	RW	0x0	In oneshot mode only the first occurrence of the SYSREF signal is used for alignment.
		[0]	SYSREF_DISABLE	RW	0x0	Enable/Disable SYSREF handling.
0x41	0x0104	SYSREF_LMFC_OFFSET				SYSREF LMFC offset
		[31:10]	Reserved	RO	0x00
		[9:0]	SYSREF_LMFC_OFFSET	RW	0x00	Offset between SYSREF event and internal LMFC event in octets.
0x42	0x0108	SYSREF_STATUS				SYSREF status
		[31:2]	Reserved	RO	0x00
		[1]	SYSREF_ALIGNMENT_ERROR	RW1C-V	0x0	Indicates that an external SYSREF event has been observed that was unaligned to a previously observed event.
		[0]	SYSREF_DETECTED	RW1C-V	0x0	Indicates that an external SYSREF event has been observed.
0x80	0x0200	LANES_DISABLE				Enabled/Disabled lanes.
		[n]	LANE_DISABLEn	RW	0x0	Enable/Disable n-th lane (0 = enabled, 1 = disabled).
0x84	0x0210	LINK_CONF0				JESD204B link configuration.
		[31:19]	Reserved	RO	0x00
		[18:16]	OCTETS_PER_FRAME	RW	0x00	Number of octets per frame - 1 (F).
		[15:10]	Reserved	RO	0x00
		[9:0]	OCTETS_PER_MULTIFRAME	RW	0x03	Number of octets per multi-frame - 1 (K x F). In 64B/66B mode represents the number of octets per extended multiblock.
0x85	0x0214	LINK_CONF1				JESD204B link configuration.
		[31:2]	Reserved	RO	0x0
		[1]	CHAR_REPLACEMENT_DISABLE	RW	0x0	Enable/Disable user data alignment character replacement (0 = enabled, 1 = disabled). Valid for 8B/10B link.
		[0]	SCRAMBLER_DISABLE	RW	0x0	Enable/Disable user data descrambling (0 = enabled, 1 = disabled).
0x86	0x0218	MULTI_LINK_DISABLE				Enable/Disable links in case of a multi-link architecture. Valid for 8B/10B link.
		[n]	LINK_DISABLEn	RW	0x0	Enable/Disable n-th link (0 = enabled, 1 = disabled).
0x87	0x021c	LINK_CONF4				JESD204B link configuration.
		[31:8]	Reserved	RO	0x0
		[7:0]	TPL_BEATS_PER_MULTIFRAME	RW	0x00	Number of beats per multi-frame - 1 (K x F / TPL_DATA_PATH_WIDTH) at interface to Transport Layer. In 64B/66B mode represents the number of octets per extended multiblock. Available starting from version 1.06.a;
0x90	0x0240	LINK_CONF2				JESD204B link configuration. Valid for 8B/10B link.
		[31:3]	Reserved	RO	0x0
		[2]	SKIP_ILAS	RW	0x0	Skip ILAS sequence during link startup.
		[1]	CONTINUOUS_ILAS	RW	0x0	Continuously transmit ILAS sequence.
		[0]	CONTINUOUS_CGS	RW	0x0	Continuously transmit CGS sequence.
0x91	0x0244	LINK_CONF3				JESD204B link configuration. Valid for 8B/10B link.
		[31:8]	Reserved	RO	0x0
		[7:0]	MFRAMES_PER_ILAS	RW	0x03	Number of multi-frames in the ILAS sequence - 1.
0x92	0x0248	MANUAL_SYNC_REQUEST				Manual synchronization request. Valid for 8B/10B link.
		[31:1]	Reserved	RO	0x0
		[0]	MANUAL_SYNC_REQUEST	W1S	0x0	Trigger manual synchronization request.
0xa0	0x0280	LINK_STATUS				JESD204B link status.
		[31:12]	Reserved	RO	0x00
		[11:4]	STATUS_SYNC	RO-V	0x??	Raw state of the external SYNC~ signals. Valid for 8B/10B link.
		[3:2]	Reserved	RO	0x00
		[1:0]	STATUS_STATE	RO-V	0x00	State of the 8B/10B link state machine. (0 = WAIT, 1 = CGS, 2 = ILAS, 3 = DATA); State of the 64B/66B link state machine. (0 = RESET, 3 = DATA)
0xc4 + 0x08*n	0x0310 +0x20*n	LANEn_ILAS0				ILAS config data for the n-th lane. Valid for 8B/10B link.
		[31:28]	Reserved	RO	0x0
		[27:24]	BID	RW	0x0	BID (Bank ID) field of the ILAS config sequence.
		[23:16]	DID	RW	0x00	DID (Device ID) field of the ILAS config sequence.
		[15:0]	Reserved	RO	0x0000
0xc5 + 0x08*n	0x0314 +0x20*n	LANEn_ILAS1				ILAS config data for the n-th lane. Valid for 8B/10B link.
		[31:29]	Reserved	RO	0x00
		[28:24]	K	RW	0x00	K (Frames per multi-frame) field of the ILAS config sequence - 1.
		[23:16]	F	RW	0x00	F (Octets per frame) field of the ILAS config sequence - 1.
		[15]	SCR	RW	0x0	SCR (Scrambling enabled) field of the ILAS config sequence.
		[14:13]	Reserved	RO	0x0
		[12:8]	L	RW	0x00	L (Number of lanes) field of the ILAS config sequence - 1.
		[7:5]	Reserved	RO	0x0
		[4:0]	LID	RW	0x00	LID (Lane ID) field of the ILAS config sequence.
0xc6 + 0x08*n	0x0318 +0x20*n	LANEn_ILAS2				ILAS config data for the n-th lane. Valid for 8B/10B link.
		[31:29]	JESDV	RW	0x0	JESDV (JESD204 version) field of the ILAS config sequence.
		[28:24]	S	RW	0x00	S (Samples per frame) field of the ILAS config sequence - 1.
		[23:21]	SUBCLASSV	RW	0x0	SUBCLASSV (JESD204B subclass) field of the ILAS config sequence.
		[20:16]	NP	RW	0x00	N' (Total number of bits per sample) field of the ILAS config sequence - 1.
		[15:14]	CS	RW	0x0	CS (Control bits per sample) field of the ILAS config sequence.
		[13]	Reserved	RO	0x0
		[12:8]	N	RW	0x00	N (Converter resolution) field of the ILAS config sequence - 1.
		[7:0]	M	RW	0x00	M (Number of converters) field of the ILAS config sequence - 1.
0xc7 + 0x08*n	0x031c +0x20*n	LANEn_ILAS3				ILAS config data for the n-th lane. Valid for 8B/10B link.
		[31:24]	FCHK	RW	0x00	FCHK (Checksum) field of the ILAS config sequence.
		[23:8]	Reserved	RO	0x0
		[7]	HD	RW	0x0	HD (High-density) field of the ILAS config sequence.
		[6:5]	Reserved	RO	0x0
		[4:0]	CF	RO	0x00	CF (control words per frame) field of the ILAS config sequence
Tue Mar 14 10:17:59 2023

DMA Controller (axi_dmac)

Click to expand regmap

0x000	0x0000	VERSION				Version of the peripheral. Follows semantic versioning. Current version 4.05.61.
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:16]	VERSION_MAJOR	RO	0x04
		[15:8]	VERSION_MINOR	RO	0x05
		[7:0]	VERSION_PATCH	RO	0x61
0x001	0x0004	PERIPHERAL_ID
		[31:0]	PERIPHERAL_ID	RO	`ID`	Value of the ID configuration parameter.
0x002	0x0008	SCRATCH
		[31:0]	SCRATCH	RW	0x00000000	Scratch register useful for debug.
0x003	0x000c	IDENTIFICATION
		[31:0]	IDENTIFICATION	RO	0x444D4143	Peripheral identification ('D', 'M', 'A', 'C').
0x004	0x0010	INTERFACE_DESCRIPTION
		[3:0]	BYTES_PER_BEAT_DEST_LOG2	R	log2(`DMA_DATA_WIDTH_DEST`/8)	Width of data bus on destination interface. Log2 of interface data widths in bytes.
		[5:4]	DMA_TYPE_DEST	R	`DMA_TYPE_DEST`	Value of `DMA_TYPE_DEST` parameter.(0 - AXI MemoryMap, 1 - AXI Stream, 2 - FIFO
		[11:8]	BYTES_PER_BEAT_SRC_LOG2	R	log2(`DMA_DATA_WIDTH_SRC`/8)	Width of data bus on source interface. Log2 of interface data widths in bytes.
		[13:12]	DMA_TYPE_SRC	R	`DMA_TYPE_SRC`	Value of `DMA_TYPE_SRC` parameter.(0 - AXI MemoryMap, 1 - AXI Stream, 2 - FIFO
		[19:16]	BYTES_PER_BURST_WIDTH	R	`BYTES_PER_BURST_WIDTH`	Value of `BYTES_PER_BURST_WIDTH` interface parameter. Log2 of the real `MAX_BYTES_PER_BURST`. The starting address of the transfer must be aligned with `MAX_BYTES_PER_BURST` to avoid crossing the 4kB address boundary.
0x020	0x0080	IRQ_MASK
		[1]	TRANSFER_COMPLETED	RW	0x1	Masks the TRANSFER_COMPLETED IRQ.
		[0]	TRANSFER_QUEUED	RW	0x1	Masks the TRANSFER_QUEUED IRQ.
0x021	0x0084	IRQ_PENDING
		[1]	TRANSFER_COMPLETED	RW1C	0x0	This bit will be asserted if a transfer has been completed and the TRANSFER_COMPLETED bit in the IRQ_MASK register is not set. Either if all bytes have been transferred or an error occurred during the transfer.
		[0]	TRANSFER_QUEUED	RW1C	0x0	This bit will be asserted if a transfer has been queued and it is possible to queue the next transfer. It can be masked out by setting the TRANSFER_QUEUED bit in the IRQ_MASK register.
0x022	0x0088	IRQ_SOURCE
		[1]	TRANSFER_COMPLETED	RO	0x0	This bit will be asserted if a transfer has been completed. Either if all bytes have been transferred or an error occurred during the transfer. Cleared together with the corresponding IRQ_PENDING bit.
		[0]	TRANSFER_QUEUED	RO	0x0	This bit will be asserted if a transfer has been queued and it is possible to queue the next transfer. Cleared together with the corresponding IRQ_PENDING bit.
0x100	0x0400	CONTROL
		[2]	HWDESC	RW	0x0	When set to 1 the scatter-gather transfers are enabled. Note, this field is only valid if the DMA channel has been configured with SG transfer support.
		[1]	PAUSE	RW	0x0	When set to 1 the currently active transfer is paused. It will be resumed once the bit is cleared again.
		[0]	ENABLE	RW	0x0	When set to 1 the DMA channel is enabled.
0x101	0x0404	TRANSFER_ID
		[1:0]	TRANSFER_ID	RO	0x00	This register contains the ID of the next transfer. The ID is generated by the DMAC and after the transfer has been started can be used to check if the transfer has finished by checking the corresponding bit in the TRANSFER_DONE register. The contents of this register is only valid if TRANSFER_SUBMIT is 0.
0x102	0x0408	TRANSFER_SUBMIT
		[0]	TRANSFER_SUBMIT	RW	0x0	Writing a 1 to this register queues a new transfer. The bit transitions back to 0 once the transfer has been queued or the DMA channel is disabled. Writing a 0 to this register has no effect.
0x103	0x040c	FLAGS
		[0]	CYCLIC	RW	`CYCLIC`	Setting this field to 1 puts the DMA transfer into cyclic mode. In cyclic mode the controller will re-start a transfer again once it has finished. In cyclic mode no end-of-transfer interrupts will be generated.
		[1]	TLAST	RW	0x1	When setting this bit for a MM to AXIS transfer the TLAST signal will be asserted during the last beat of the transfer. For AXIS to MM transfers the TLAST signal from the AXIS interface is monitored. After its occurrence all descriptors are ignored until this bit is set.
		[2]	PARTIAL_REPORTING_EN	RW	0x0	When setting this bit the length of partial transfers caused eventually by TLAST will be recorded.
0x104	0x0410	DEST_ADDRESS
		[31:0]	DEST_ADDRESS	RW	0x00000000	This register contains the destination address of the transfer. The address needs to be aligned to the bus width. This register is only valid if the DMA channel has been configured for write to memory support.
0x105	0x0414	SRC_ADDRESS
		[31:0]	SRC_ADDRESS	RW	0x00000000	This register contains the source address of the transfer. The address needs to be aligned to the bus width. This register is only valid if the DMA channel has been configured for read from memory support.
0x106	0x0418	X_LENGTH
		[23:0]	X_LENGTH	RW	{log2(max( `DMA_DATA_WIDTH_SRC`, `DMA_DATA_WIDTH_DEST` )/8){1'b1}}	Number of bytes to transfer - 1.
0x107	0x041c	Y_LENGTH
		[23:0]	Y_LENGTH	RW	0x000000	Number of rows to transfer - 1. Note, this field is only valid if the DMA channel has been configured with 2D transfer support.
0x108	0x0420	DEST_STRIDE
		[23:0]	DEST_STRIDE	RW	0x000000	The number of bytes between the start of one row and the next row for the destination address. Needs to be aligned to the bus width. Note, this field is only valid if the DMA channel has been configured with 2D transfer support and write to memory support.
0x109	0x0424	SRC_STRIDE
		[23:0]	SRC_STRIDE	RW	0x000000	The number of bytes between the start of one row and the next row for the source address. Needs to be aligned to the bus width. Note, this field is only valid if the DMA channel has been configured with 2D transfer and read from memory support.
0x10a	0x0428	TRANSFER_DONE				If bit x is set in this register the transfer with ID x has been completed. The bit will automatically be cleared when a new transfer with this ID is queued and will be set when the transfer has been completed.
		[0]	TRANSFER_0_DONE	RO	0x0	If this bit is set the transfer with ID 0 has been completed.
		[1]	TRANSFER_1_DONE	RO	0x0	If this bit is set the transfer with ID 1 has been completed.
		[2]	TRANSFER_2_DONE	RO	0x0	If this bit is set the transfer with ID 2 has been completed.
		[3]	TRANSFER_3_DONE	RO	0x0	If this bit is set the transfer with ID 3 has been completed.
		[31]	PARTIAL_TRANSFER_DONE	RO	0x0	If this bit is set at least one partial transfer was transferred. This field will reset when the ENABLE control bit is reset or when all information on partial transfers was read through PARTIAL_TRANSFER_LENGTH and PARTIAL_TRANSFER_ID registers.
0x10b	0x042c	ACTIVE_TRANSFER_ID
		[4:0]	ACTIVE_TRANSFER_ID	RO	0x00	ID of the currently active transfer. When no transfer is active this register will be equal to the TRANSFER_ID register.
0x10c	0x0430	STATUS
		[31:0]	RESERVED	RO	0x00000000	This register is reserved for future usage. Reading it will always return 0.
0x10d	0x0434	CURRENT_DEST_ADDRESS
		[31:0]	CURRENT_DEST_ADDRESS	RO	0x00000000	Address to which the next data sample is written to. This register is only valid if the DMA channel has been configured for write to memory support.
0x10e	0x0438	CURRENT_SRC_ADDRESS
		[31:0]	CURRENT_SRC_ADDRESS	RO	0x00000000	Address form which the next data sample is read. This register is only valid if the DMA channel has been configured for read from memory support.
0x112	0x0448	TRANSFER_PROGRESS
		[23:0]	TRANSFER_PROGRESS	RO	0x000000	This field presents the number of bytes transferred to the destination for the current transfer. This register will be cleared once the transfer completes. This should be used for debugging purposes only.
0x113	0x044c	PARTIAL_TRANSFER_LENGTH
		[31:0]	PARTIAL_LENGTH	RO	0x00000000	Length of the partial transfer in bytes. Represents the number of bytes received until the moment of TLAST assertion. This will be smaller than the programmed length from the X_LENGTH and Y_LENGTH registers.
0x114	0x0450	PARTIAL_TRANSFER_ID				Must be read after the PARTIAL_TRANSFER_LENGTH registers.
		[1:0]	PARTIAL_TRANSFER_ID	RO	0x0	ID of the transfer that was partial.
0x115	0x0454	DESCRIPTOR_ID
		[31:0]	DESCRIPTOR_ID	RO	0x00000000	ID of the descriptor that points to the current memory segment being transferred. If HWDESC is set to 0, then this register returns 0.
0x11f	0x047c	SG_ADDRESS
		[31:0]	SG_ADDRESS	RW	0x00000000	This register contains the starting address of the scatter-gather transfer. The address needs to be aligned to the bus width. This register is only valid if the DMA channel has been configured with SG transfer support.
0x124	0x0490	DEST_ADDRESS_HIGH
		[31:0]	DEST_ADDRESS_HIGH	RW	0x00000000	This register contains the HIGH segment of the destination address of the transfer. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if DMA channel has been configured for write to memory support.
0x125	0x0494	SRC_ADDRESS_HIGH
		[31:0]	SRC_ADDRESS_HIGH	RW	0x00000000	This register contains the HIGH segment of the source address of the transfer. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support.
0x126	0x0498	CURRENT_DEST_ADDRESS_HIGH
		[31:0]	CURRENT_DEST_ADDRESS_HIGH	RO	0x00000000	HIGH segment of the address to which the next data sample is written to. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for write to memory support.
0x127	0x049c	CURRENT_SRC_ADDRESS_HIGH
		[31:0]	CURRENT_SRC_ADDRESS_HIGH	RO	0x00000000	HIGH segment of the address from which the next data sample is read. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support.
0x12f	0x04bc	SG_ADDRESS_HIGH
		[31:0]	SG_ADDRESS_HIGH	RW	0x00000000	HIGH segment of the starting address of the scatter-gather transfer. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured with SG transfer support.
Thu Feb 1 12:18:03 2024

Fan Controller (axi_fan_control)

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0x00	0x0000	VERSION				Version of the peripheral. Follows semantic versioning. Current version 1.00.a.
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:16]	VERSION_MAJOR	RO	0x0001
		[15:8]	VERSION_MINOR	RO	0x00
		[7:0]	VERSION_PATCH	RO	0x61
0x01	0x0004	PERIPHERAL_ID
		[31:0]	PERIPHERAL_ID	RO	`ID`	Value of the ID configuration parameter.
0x02	0x0008	SCRATCH
		[31:0]	SCRATCH	RW	0x00000000	Scratch register useful for debug.
0x03	0x000c	IDENTIFICATION
		[31:0]	IDENTIFICATION	RO	0x46414E43	Peripheral identification ('F', 'A', 'N', 'C').
0x10	0x0040	IRQ_MASK
		[3]	NEW_TACHO_MEASUREMENT	RW	0x1	Masks the TACHO_MEASUREMENT_DONE IRQ.
		[2]	TEMP_INCREASE	RW	0x1	Masks the TEMP_INCREASE IRQ.
		[1]	TACHO_ERR	RW	0x1	Masks the TACHO_ERR IRQ.
		[0]	PWM_CHANGED	RW	0x1	Masks the PWM_CHANGED IRQ.
0x11	0x0044	IRQ_PENDING
		[3]	NEW_TACHO_MEASUREMENT	RW1C	0x0	This bit will be asserted when the hardware has written a new value to the TACHO_MEASUREMENT register if the NEW_TACHO_MEASUREMENT bit in the IRQ_MASK register is not set.
		[2]	TEMP_INCREASE	RW1C	0x0	This bit will be asserted whenever the HW decides to increase the PWM duty-cycle, indicating a rise in temperature, and if the TEMP_INCREASE bit in the IRQ_MASK register is not set.
		[1]	TACHO_ERR	RW1C	0x0	This bit will be asserted when a fault related to the tacho signal is detected. This can either mean that the tacho has not toggled in 5 seconds or that the period of the tacho signal is no longer whithin the defined valid interval. Also, the TACHO_ERR bit in the IRQ_MASK register must not be set.
		[0]	PWM_CHANGED	RW1C	0x0	This bit will be asserted when a 5 second delay expires after the PWM width was changed. The delay is used to allow the fan rotation speed to stabilize. Also, the PWM_CHANGED bit in the IRQ_MASK register must not be set.
0x12	0x0048	IRQ_SOURCE
		[3]	NEW_TACHO_MEASUREMENT	RO	0x0	This bit will be asserted when the hardware has written a new value to the TACHO_MEASUREMENT register.
		[2]	TEMP_INCREASE	RO	0x0	This bit will be asserted whenever the hardware decides to increase the PWM duty-cycle indicating a rise in temperature.
		[1]	TACHO_ERR	RO	0x0	This bit will be asserted when a fault related to the tacho signal is detected. This can either mean that the tacho has not toggled in 5 seconds or that the period of the tacho signal is no longer whithin the defined valid interval.
		[0]	PWM_CHANGED	RO	0x0	This bit will be asserted when a 5 second delay expires after the PWM width was changed. The delay is used to allow the fan rotation speed to stabilize.
0x20	0x0080	REG_RSTN
		[0]	RSTN	RW	0x0	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x21	0x0084	PWM_WIDTH
		[31:0]	PWM_WIDTH	RW	`PWM_PERIOD`	This register contains the width of the PWM output signal. By default its value is established by the hardware after reading the temperature. By writing to this register the software can change the value however this is only possible if the requested value is greater than the value selected by the hardware and not exceeding the PWM period.
0x22	0x0088	TACHO_PERIOD
		[31:0]	TACHO_PERIOD	RW	0x00000000	After using the PWM_WIDTH register to request a different duty-cycle, the software can use this register to define the target period of the tacho signal. This is used together with the TACHO_TOLERANCE register to define an interval for the tacho signal. This register must be written before the TACHO_TOLERANCE register. The hardware will then use this interval to monitor the tacho signal coming from the fan.
0x23	0x008c	TACHO_TOLERANCE
		[31:0]	TACHO_TOLERANCE	RW	0x00000000	This register is used together with the TACHO_PERIOD register to define an interval for the fan's tacho signal. Writing to this register enables the hardware to start monitoring the tacho signal and so it must be written after the TACHO_PERIOD register.
0x24	0x0090	TEMP_DATA_SOURCE
		[31:0]	TEMP_DATA_SOURCE	RO	`INTERNAL_SYSMONE`	This register copies the value from the INTERNAL_SYSMONE register and is used to inform the software what the source of the temperature information is.
0x30	0x00c0	PWM_PERIOD
		[31:0]	PWM_PERIOD	RO	0x4E20	This register contains the period for the PWM output signal. Derived from the PWM_FREQUENCY_HZ parameter.
0x31	0x00c4	TACHO_MEASUREMENT
		[31:0]	TACHO_MEASUREMENT	RO	0x00000000	This register contains the measurement results of the tacho signal period performed by the hardware.
0x32	0x00c8	TEMPERATURE
		[31:0]	TEMPERATURE	RO	0x00000000	This register contains the latest temperature reading from the SYSMONE primitive.
0x40	0x0100	TEMP_00_H
		[31:0]	TEMP_00_H	RW	`TEMP_00_H`	Temperature threshold below which PWM should be 0%
0x41	0x0104	TEMP_25_L
		[31:0]	TEMP_25_L	RW	`TEMP_25_L`	Temperature threshold above which PWM should be 25%
0x42	0x0108	TEMP_25_H
		[31:0]	TEMP_25_H	RW	`TEMP_25_H`	Temperature threshold below which PWM should be 25%
0x43	0x010c	TEMP_50_L
		[31:0]	TEMP_50_L	RW	`TEMP_50_L`	Temperature threshold above which PWM should be 50%
0x44	0x0110	TEMP_50_H
		[31:0]	TEMP_50_H	RW	`TEMP_50_H`	Temperature threshold below which PWM should be 50%
0x45	0x0114	TEMP_75_L
		[31:0]	TEMP_75_L	RW	`TEMP_75_L`	Temperature threshold above which PWM should be 75%
0x46	0x0118	TEMP_75_H
		[31:0]	TEMP_75_H	RW	`TEMP_75_H`	Temperature threshold below which PWM should be 75%
0x47	0x011c	TEMP_100_L
		[31:0]	TEMP_100_L	RW	`TEMP_100_L`	Temperature threshold above which PWM should be 100%
0x50	0x0140	TACHO_25
		[31:0]	TACHO_25	RW	`TACHO_T25`	Nominal tacho period at 25% PWM
0x51	0x0144	TACHO_50
		[31:0]	TACHO_50	RW	`TACHO_T50`	Nominal tacho period at 50% PWM
0x52	0x0148	TACHO_75
		[31:0]	TACHO_75	RW	`TACHO_T75`	Nominal tacho period at 75% PWM
0x53	0x014c	TACHO_100
		[31:0]	TACHO_100	RW	`TACHO_T100`	Nominal tacho period at 100% PWM
0x54	0x0150	TACHO_25_TOL
		[31:0]	TACHO_25_TOL	RW	`TACHO_T25` `*TACHO_TOL_PERCENT` `/100`	Tolerance for the 25% PWM tacho period
0x55	0x0154	TACHO_50_TOL
		[31:0]	TACHO_50_TOL	RW	`TACHO_T50` `*TACHO_TOL_PERCENT` `/100`	Tolerance for the 50% PWM tacho period
0x56	0x0158	TACHO_75_TOL
		[31:0]	TACHO_75_TOL	RW	`TACHO_T75` `*TACHO_TOL_PERCENT` `/100`	Tolerance for the 75% PWM tacho period
0x57	0x015c	TACHO_100_TOL
		[31:0]	TACHO_100_TOL	RW	`TACHO_T100` `*TACHO_TOL_PERCENT` `/100`	Tolerance for the 100% PWM tacho period
Tue Mar 14 10:17:59 2023

System ID (axi_system_id)

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0x00	0x0000	VERSION				Version of the peripheral. Follows semantic versioning. Current version 1.00.a.
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:16]	VERSION_MAJOR	RO	0x0001
		[15:8]	VERSION_MINOR	RO	0x00
		[7:0]	VERSION_PATCH	RO	0x61
0x01	0x0004	PERIPHERAL_ID
		[31:0]	PERIPHERAL_ID	RO	`ID`	Value of the ID configuration parameter.
0x02	0x0008	SCRATCH
		[31:0]	SCRATCH	RW	0x00000000	Scratch register useful for debug.
0x03	0x000c	IDENTIFICATION
		[31:0]	IDENTIFICATION	RO	0x53594944	Peripheral identification ('S', 'Y', 'I', 'D').
0x200	0x0800	SYSROM_START
		[31:0]	SYSROM_START	RO	`N/A`	Start of register space for System ROM. Initialized at synthesis.
0x400	0x1000	PRROM_START
		[31:0]	SYSROM_START	RO	`N/A`	Start of register space for partial reconfiguration block ROM. Initialized at synthesis.
Tue Mar 14 10:17:59 2023

Clock Generator (axi_clkgen)

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0x0010	0x0040	REG_RSTN				Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[1]	MMCM_RSTN	RW	0x0	MMCM reset (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
		[0]	RSTN	RW	0x0	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x0011	0x0044	REG_CLK_SEL				Clock Select
		[0]	CLK_SEL	RW	0x0	Select betwen CLKIN1 (0x0) or CLKIN2 (0x1) input clock for the MMCM
0x0017	0x005c	REG_MMCM_STATUS				MMCM Status
		[0]	MMCM_LOCKED	RO	0x0	LOCKED status of the MMCM
0x001c	0x0070	REG_DRP_CNTRL				ADC Interface Control & Status
		[28]	DRP_RWN	RW	0x0	DRP read (0x1) or write (0x0) select (does not include GTX lanes).
		[27:16]	DRP_ADDRESS[11:0]	RW	0x000	DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes).
		[15:0]	DRP_WDATA[15:0]	RW	0x0000	DRP write data (does not include GTX lanes).
0x001d	0x0074	REG_DRP_STATUS				MMCM Status
		[17]	MMCM_LOCKED	RO	0x0	LOCKED status of the MMCM
		[16]	DRP_STATUS	RO	0x0	If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes).
		[15:0]	DRP_RDATA	RO	0x0000	DRP read data (does not include GTX lanes).
0x0050	0x0140	REG_FPGA_VOLTAGE				FPGA device voltage information
		[15:0]	FPGA_VOLTAGE	RO	0x0	The voltage of the FPGA device in mv
Tue Mar 14 10:17:59 2023

Clock Monitor (axi_clock_monitor)

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0x0000	0x0000	PCORE_VERSION				PCORE Version Registers
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:0]	PCORE_VERSION	RO	0x00000001	PCORE Version number
0x0001	0x0004	ID				ID Registers
		[31:0]	ID	RW	0x00000000	Instance identifier number
0x0003	0x000c	NUM_OF_CLOCKS				Number of Clocks Registers
		[31:0]	NUM_OF_CLOCKS	RW	0x00000008	Number of clock inputs
0x0004	0x0010	OUT_RESET				Reset Control Registers
		0x0	reset	RW	0x00	Control the out reset signal
0x0010	0x0040	CLOCK_0				Measured clock_0
		[31:0]	clock_0	RO	0x00000000	Measured frequency of clock_0
0x0011	0x0044	CLOCK_1				Measured clock_1
		[31:0]	clock_1	RO	0x00000000	Measured frequency of clock_1
0x0012	0x0048	CLOCK_2				Measured clock_2
		[31:0]	clock_2	RO	0x00000000	Measured frequency of clock_2
0x0013	0x004c	CLOCK_3				Measured clock_3
		[31:0]	clock_3	RO	0x00000000	Measured frequency of clock_3
0x0014	0x0050	CLOCK_4				Measured clock_4
		[31:0]	clock_4	RO	0x00000000	Measured frequency of clock_4
0x0015	0x0054	CLOCK_5				Measured clock_5
		[31:0]	clock_5	RO	0x00000000	Measured frequency of clock_5
0x0016	0x0058	CLOCK_6				Measured clock_6
		[31:0]	clock_6	RO	0x00000000	Measured frequency of clock_6
0x0017	0x005c	CLOCK_7				Measured clock_7
		[31:0]	clock_7	RO	0x00000000	Measured frequency of clock_7
0x0018	0x0060	CLOCK_8				Measured clock_8
		[31:0]	clock_8	RO	0x00000000	Measured frequency of clock_8
0x0019	0x0064	CLOCK_9				Measured clock_9
		[31:0]	clock_9	RO	0x00000000	Measured frequency of clock_9
0x001A	0x0068	CLOCK_10				Measured clock_10
		[31:0]	clock_10	RO	0x00000000	Measured frequency of clock_10
0x001B	0x006c	CLOCK_11				Measured clock_11
		[31:0]	clock_11	RO	0x00000000	Measured frequency of clock_11
0x001C	0x0070	CLOCK_12				Measured clock_12
		[31:0]	clock_12	RO	0x00000000	Measured frequency of clock_12
0x001D	0x0074	CLOCK_13				Measured clock_13
		[31:0]	clock_13	RO	0x00000000	Measured frequency of clock_13
0x001E	0x0078	CLOCK_14				Measured clock_14
		[31:0]	clock_14	RO	0x00000000	Measured frequency of clock_14
0x001F	0x007c	CLOCK_15				Measured clock_15
		[31:0]	clock_15	RO	0x00000000	Measured frequency of clock_15
Tue Mar 14 10:17:59 2023

HDMI Transmit (axi_hdmi_tx)

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0x0010	0x0040	REG_RSTN				HDMI Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[0]	RSTN	RW	0x0	Reset, a common reset is used for all the interface modules, The default is reset (0x0), software must write 0x1 to bring up the core.
0x0011	0x0044	REG_CNTRL1				HDMI Interface Control & Status
		[2]	SS_BYPASS	RW	0x0	If set (0x1) bypasses the chroma sub-sampler. This is primarily intended to be used to send the test-pattern directly to the HDMI transmitter without modifying it.
		[1]	RESERVED	RO	0x0	Reserved
		[0]	CSC_BYPASS	RW	0x0	If set (0x1) bypasses color space conversion (if equipped). And depending on its value, the default value of color space boundaries is set in the REG_CLIPP_MAX and REG_CLIPP_MIN registers.
0x0012	0x0048	REG_CNTRL2				HDMI Interface Control & Status
		[1:0]	SOURCE_SEL	RW	0x0	Select the HDMI data source- register constant (0x3), incr-pattern (0x2), input (0x1) or disabled (0x0).
0x0013	0x004c	REG_CNTRL3				HDMI Interface Control & Status
		[23:0]	CONST_RGB[23:0]	RW	0x000000	This is the RGB value transmitted, if the source is constant (see above).
0x0015	0x0054	REG_CLK_FREQ				HDMI Interface Control & Status
		[31:0]	CLK_FREQ[31:0]	RO	0x00000000	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016	0x0058	REG_CLK_RATIO				HDMI Interface Control & Status
		[31:0]	CLK_RATIO[31:0]	RO	0x00000000	Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0017	0x005c	REG_STATUS				ADC Interface Control & Status
		[0]	STATUS	RO	0x0	Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018	0x0060	REG_VDMA_STATUS				HDMI Interface Control & Status
		[1]	VDMA_OVF	RW1C	0x0	If set, indicates vdma overflow.
		[0]	VDMA_UNF	RW1C	0x0	If set, indicates vdma underflow.
0x0019	0x0064	REG_TPM_STATUS				HDMI Interface Control & Status
		[1]	HDMI_TPM_OOS	RW1C	0x0	If set, indicates TPM OOS at the HDMI interface.
		[0]	VDMA_TPM_OOS	RW1C	0x0	If set, indicates TPM OOS at the VDMA interface.
0x001a	0x0068	REG_CLIPP_MAX				HDMI Interface Control & Status
		[23:16]	R_MAX/Cr_MAX	RW	0xF0	Defines the maximum value for clipping the red or red-difference chroma component. Default value are 0xf0 for red-difference chroma and 0xfe for red.
		[16:8]	G_MAX/Y_MAX	RW	0xEB	Defines the maximum value for clipping the green or luma component. Default values are 0xeb for luma and and 0xfe for green.
		[7:0]	B_MAX/Cb_MAX	RW	0xF0	Defines the maximum value for clipping the blue or blue-difference chroma component. Default value are 0xf0 for blue-difference chroma and 0xfe for blue.
0x001b	0x006c	REG_CLIPP_MIN				HDMI Interface Control & Status
		[23:16]	R_MIN/Cr_MIN	RW	0x10	Defines the minimum value for clipping the red or red-difference chroma component. Default value are 0x10 for red-difference chroma and 0x01 for red.
		[16:8]	G_MIN/Y_MIN	RW	0x10	Defines the minimum value for clipping the green or luma component. Default values are 0x10 for luma and and 0x01 for green.
		[7:0]	B_MIN/Cb_MIN	RW	0x10	Defines the minimum value for clipping the blue or blue-difference chroma component. Default value are 0x10 for blue-difference chroma and 0x01 for blue.
0x0100	0x0400	REG_HSYNC_1				HDMI Interface Control & Status
		[31:16]	H_LINE_ACTIVE[15:0]	RW	0x0000	This is the horizontal line active pixel width (active resolution length). e.g. 1920 (1080p)
		[15:0]	H_LINE_WIDTH[15:0]	RW	0x0000	This is the horizontal line width (no. of pixel clocks per line). e.g. 2200 (1080p)
0x0101	0x0404	REG_HSYNC_2				HDMI Interface Control & Status
		[15:0]	H_SYNC_WIDTH[15:0]	RW	0x0000	This is the horizontal sync width (no. of pixel clocks). e.g. 44 (1080p)
0x0102	0x0408	REG_HSYNC_3				HDMI Interface Control & Status
		[31:16]	H_ENABLE_MAX[15:0]	RW	0x0000	This is the horizontal data enable maximum. It is the sum of H_ENABLE_MIN and the active pixel width. e.g. 2112 (192 + 1920) (1080p)
		[15:0]	H_ENABLE_MIN[15:0]	RW	0x0000	This is the horizontal data enable minimum. It is the sum of horizontal back porch (number of clock cycles between the falling edge of HSYNC to the rising edge of DE) and the sync width. e.g. 192 (44 + 148) (1080p)
0x0110	0x0440	REG_VSYNC_1				HDMI Interface Control & Status
		[31:16]	V_FRAME_ACTIVE[15:0]	RW	0x0000	This is the vertical frame active line width (active resolution height). e.g. 1080 (1080p)
		[15:0]	V_FRAME_WIDTH[15:0]	RW	0x0000	This is the vertical frame width (no. of lines per frame). e.g. 1125 (1080p)
0x0111	0x0444	REG_VSYNC_2				HDMI Interface Control & Status
		[15:0]	V_SYNC_WIDTH[15:0]	RW	0x0000	This is the vertical sync width (no. of lines). e.g. 5 (1080p)
0x0112	0x0448	REG_VSYNC_3				HDMI Interface Control & Status
		[31:16]	V_ENABLE_MAX[15:0]	RW	0x0000	This is the vertical data enable maximum. It is the sum of V_ENABLE_MIN and the active pixel height. e.g. 1121 (41 + 1080) (1080p)
		[15:0]	V_ENABLE_MIN[15:0]	RW	0x0000	This is the vertical data enable minimum. It is the sum of vertical back porch (number of lines between the falling edge of VSYNC to the rising edge of DE) and the sync width. e.g. 41 (36 + 5) (1080p)
Tue Mar 14 10:17:59 2023

HDMI Receive (axi_hdmi_rx)

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0x0010	0x0040	REG_RSTN				HDMI Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[0]	RSTN	RW	0x0	Reset, a common reset is used for all the interface modules, The default is reset (0x0), software must write 0x1 to bring up the core.
0x0011	0x0044	REG_CNTRL				HDMI Interface Control & Status
		[3]	EDGE_SEL	RW	0x0	If set (0x1), incoming data is registered on the falling edge of the clock first. The default uses rising edge.
		[2]	BGR	RW	0x0	If set (0x1), output BGR. The default is RGB.
		[1]	PACKED	RW	0x0	If set (0x1) pack 24bit RGB data on 32bit dwords. The default pads the MSB to zeros.
		[0]	CSC_BYPASS	RW	0x0	If set (0x1) bypasses color space conversion (if equipped).
0x0015	0x0054	REG_CLK_FREQ				HDMI Interface Control & Status
		[31:0]	CLK_FREQ[31:0]	RO	0x00000000	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016	0x0058	REG_CLK_RATIO				HDMI Interface Control & Status
		[31:0]	CLK_RATIO[31:0]	RO	0x00000000	Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0018	0x0060	REG_VDMA_STATUS				HDMI Interface Control & Status
		[1]	VDMA_OVF	RW1C	0x0	If set, indicates vdma overflow.
		[0]	VDMA_UNF	RW1C	0x0	If set, indicates vdma underflow.
0x0019	0x0064	REG_TPM_STATUS1				HDMI Interface Control & Status
		[1]	HDMI_TPM_OOS	RW1C	0x0	If set, indicates TPM OOS at the HDMI interface.
0x0020	0x0080	REG_TPM_STATUS2				HDMI Interface Control & Status
		[3]	VS_OOS	RW1C	0x0	If set, indicates VSYNC OOS - the core is unabled to detect/track VSYNC. Consecutive frames have different number of lines.
		[2]	HS_OOS	RW1C	0x0	If set, indicates HSYNC OOS - the core is unabled to detect/track HSYNC. Consecutive lines have different lengths.
		[1]	VS_MISMATCH	RW1C	0x0	If set, indicates received (detected) & programmed VSYNC (number of lines) mismatch. Incoming frames are stable but not the expected resolution.
		[0]	HS_MISMATCH	RW1C	0x0	If set, indicates received (detected) & programmed HSYNC (number of pixels) mismatch. Incoming frames are stable but not the expected resolution.
0x0100	0x0400	REG_HVCOUNTS1				HDMI Interface Control & Status
		[31:16]	VS_COUNT[15:0]	RW	0x0000	This is the expected active horizontal pixel lines (active resolution length). e.g. 1080 (1080p)
		[15:0]	HS_COUNT[15:0]	RW	0x0000	This is the expected horizontal pixel count (no. of pixel clocks per line). e.g. 1920 (1080p)
0x0101	0x0404	REG_HVCOUNTS2				HDMI Interface Control & Status
		[31:16]	VS_COUNT[15:0]	RO	0x0000	This is the detected horizontal active pixel lines (active resolution length). This field is valid only if VS_OOS is zero.
		[15:0]	HS_COUNT[15:0]	RO	0x0000	This is the detected horizontal pixel count (no. of pixel clocks per line). This field is valid only if HS_OOS is zero.
Tue Mar 14 10:17:59 2023

General Purpose Registers (axi_gpreg)

Click to expand regmap

0x0100	0x0400	REG_IO_ENB				IO control register
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:0]	IO_ENB	RW	0x00000000	IO control register (use as tri-state control, logic depends on the buffer type).
0x0101	0x0404	REG_IO_OUT				IO output register
		[31:0]	IO_ENB	RW	0x00000000	IO output register.
0x0102	0x0408	REG_IO_IN				IO input register
		[31:0]	IO_IN	RO	0x00000000	IO input register.
0x0110	0x0440	REG_*				Channel 1, similar to register 0x100 to 0x10f.
0x0120	0x0480	REG_*				Channel 2, similar to register 0x100 to 0x10f.
0x01f0	0x07c0	REG_*				Channel 15, similar to register 0x100 to 0x10f.
0x0200	0x0800	REG_CM_RESET				Reset register
		[0]	CM_RESET_N	RW	0x0	Reset register (write a 0x01 to bring core out of reset).
0x0202	0x0808	REG_CM_COUNT				Clock count register
		[31:0]	CM_CLK_COUNT	RO	0x00000000	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz.
0x0210	0x0840	REG_*				Channel 1, similar to register 0x200 to 0x20f.
0x0220	0x0880	REG_*				Channel 2, similar to register 0x200 to 0x20f.
0x02f0	0x0bc0	REG_*				Channel 15, similar to register 0x200 to 0x20f.
Tue Mar 14 10:17:59 2023

SPI Engine (axi_spi_engine)

Click to expand regmap

0x00	0x0000	VERSION				Version of the peripheral. Follows semantic versioning. Current version 1.00.71.
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:16]	VERSION_MAJOR	RO	0x01
		[15:8]	VERSION_MINOR	RO	0x00
		[7:0]	VERSION_PATCH	RO	0x71
0x01	0x0004	PERIPHERAL_ID
		[31:0]	PERIPHERAL_ID	RO	`ID`	Value of the ID configuration parameter. In case of multiple instances, each instance will have a unique ID.
0x02	0x0008	SCRATCH
		[31:0]	SCRATCH	RW	0x00000000	Scratch register useful for debug.
0x03	0x000c	DATA_WIDTH
		[31:0]	DATA_WIDTH	RO	0x00000008	Data width of the SDI/SDO parallel interface. It is equal with the maximum supported transfer length in bits.
0x10	0x0040	ENABLE
		[31:0]	ENABLE	RW	0x00000001	Enable register. If the enable bit is set to 1 the internal state of the peripheral is reset. For proper operation, the bit needs to be set to 0.
0x20	0x0080	IRQ_MASK
		[0]	CMD_ALMOST_EMPTY	RW	0x00	If set to 0 the CMD_ALMOST_EMPTY interrupt is masked.
		[1]	SDO_ALMOST_EMPTY	RW	0x00	If set to 0 the SDO_ALMOST_EMPTY interrupt is masked.
		[2]	SDI_ALMOST_FULL	RW	0x00	If set to 0 the SDI_ALMOST_FULL interrupt is masked.
		[3]	SYNC_EVENT	RW	0x00	If set to 0 the SYNC_EVENT interrupt is masked.
0x21	0x0084	IRQ_PENDING
		[31:0]	IRQ_PENDING	RW1C	0x00000000	Pending IRQs with mask.
0x22	0x0088	IRQ_SOURCE
		[31:0]	IRQ_SOURCE	RO	0x00000000	Pending IRQs without mask.
0x30	0x00c0	SYNC_ID
		[31:0]	SYNC_ID	RO	0x00000000	Last synchronization event ID received from the SPI engine control interface.
0x34	0x00d0	CMD_FIFO_ROOM
		[31:0]	CMD_FIFO_ROOM	RO	0x????????	Number of free entries in the command FIFO. The reset value of the CMD_FIFO_ROOM register depends on the setting of the CMD_FIFO_ADDRESS_WIDTH parameter.
0x35	0x00d4	SDO_FIFO_ROOM
		[31:0]	SDO_FIFO_ROOM	RO	0x????????	Number of free entries in the serial-data-out FIFO. The reset value of the SDO_FIFO_ROOM register depends on the setting of the SDO_FIFO_ADDRESS_WIDTH parameter.
0x36	0x00d8	SDI_FIFO_LEVEL
		[31:0]	SDI_FIFO_LEVEL	RO	0x00000000	Number of valid entries in the serial-data-in FIFO.
0x38	0x00e0	CMD_FIFO
		[31:0]	CMD_FIFO	WO	0x?????????	Command FIFO register. Writing to this register inserts an entry into the command FIFO. Writing to this register when the command FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
0x39	0x00e4	SDO_FIFO
		[31:0]	SDO_FIFO	WO	0x?????????	SDO FIFO register. Writing to this register inserts an entry into the SDO FIFO. Writing to this register when the SDO FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
0x3a	0x00e8	SDI_FIFO
		[31:0]	SDI_FIFO	RO	0x?????????	SDI FIFO register. Reading from this register removes the first entry from the SDI FIFO. Reading this register when the SDI FIFO is empty will return undefined data. Writing to it has no effect.
0x3c	0x00f0	SDI_FIFO_PEEK
		[31:0]	SDI_FIFO_PEEK	RO	0x?????????	SDI FIFO peek register. Reading from this register returns the first entry from the SDI FIFO, but without removing it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined data. Writing to it has no effect.
0x40	0x0100	OFFLOAD0_EN
		[31:0]	OFFLOAD0_EN	RW	0x00000000	Set this bit to enable the offload module.
0x41	0x0104	OFFLOAD0_STATUS
		[31:0]	OFFLOAD0_STATUS	RO	0x00000000	Offload status register.
0x42	0x0108	OFFLOAD0_MEM_RESET
		[31:0]	OFFLOAD0_MEM_RESET	WO	0x00000000	Reset the memory of the offload module.
0x44	0x0110	OFFLOAD0_CDM_FIFO
		[31:0]	OFFLOAD0_CDM_FIFO	WO	0x????????	Offload command FIFO register. Writing to this register inserts an entry into the command FIFO of the offload module. Writing to this register when the command FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
0x45	0x0114	OFFLOAD0_SDO_FIFO
		[31:0]	OFFLOAD0_SDO_FIFO	WO	0x????????	Offload SDO FIFO register. Writing to this register inserts an entry into the offload SDO FIFO. Writing to this register when the SDO FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000.
Tue Mar 14 10:17:59 2023

Xilinx XCVR (axi_xcvr) Regmap

Click to expand regmap

0x0000	0x0000	VERSION				Version Register
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:0]	VERSION	RO	0x00	Version number.
0x0001	0x0004	ID				Instance Identification Register
		[31:0]	ID	RO	0x00	Instance identifier number.
0x0002	0x0008	SCRATCH				Scratch (GP R/W) Register
		[31:0]	SCRATCH	RW	0x00	Scratch register.
0x0004	0x0010	RESETN				Reset Control Register
		[1]	BUFSTATUS_RST	RW	0x00	Initially this flag is held in reset with value 0x1, in order for a user to see the RX BUFSTATUS, this flag needs to be set to 0x0.
		[0]	RESETN	RW	0x00	If clear, link is held in reset, set this bit to 0x1 to activate link. Note that the reference clock and DRP clock must be active before setting this bit.
0x0005	0x0014	STATUS				Status Reporting Register
		[6:5]	BUFSTATUS	RO	0x00	BUFSTATUS provides status for either the RX buffer or the TX buffer. If BUFSTATUS is referring to the TX buffer, once BUFSTATUS is set High it remains High until RESETN is activated. Else if BUFSTATUS is referring to the RX buffer, once BUFSTSTATUS is High it can be cleared using BUFSTATUS_RST. If BUFTATUS[6] is 0x1 the internal FIFO overflows and when the BUFSTATUS[5] is 0x1 the internal FIFO underflows. Available from version 17.5.a. For more information consult the transceiver user guide(search for RXBUFSTATUS/TXBUFSTATUS).
		[4]	PLL_LOCK_N	RO	0x00	After setting the RESETN bit above, this bit must clear. If does not clears, indicates the CPLL/QPLL did not locked. Available from version 17.4.a
		[0]	STATUS	RO	0x00	After setting the RESETN bit above, wait for this bit to set. If set, indicates successful link activation.
0x0007	0x001c	FPGA_INFO				FPGA device information Xilinx encoded values
		[31:24]	FPGA_TECHNOLOGY	RO	0x00	Encoded value describing the technology/generation of the FPGA device (e.g, 7series, ultrascale)
		[23:16]	FPGA_FAMILY	RO	0x00	Encoded value describing the family variant of the FPGA device(e.g., zynq, kintex, virtex)
		[15:8]	SPEED_GRADE	RO	0x00	Encoded value describing the FPGA's speed-grade
		[7:0]	DEV_PACKAGE	RO	0x00	Encoded value describing the device package. The package might affect high-speed interfaces
0x0008	0x0020	CONTROL				Transceiver Control Register
		[12]	LPM_DFE_N	RW	0x00	Transceiver primitive control, refer Xilinx documentation.
		[10:8]	RATE[2:0]	RW	0x00	Transceiver primitive control, refer Xilinx documentation.
		[5:4]	SYSCLK_SEL[1:0]	RW	0x00	For GTX drives directly the (RX/TX)SYSCLKSEL pin of the transceiver. Refer to Xilinx documentation. For GTH/GTY drives directly the (RX/TX)PLLCLKSEL pin of the transceiver and indirectly the (RX/TX)SYSCLKSEL pin of the transceiver see Table 1.
		[2:0]	OUTCLK_SEL[2:0]	RW	0x00	Transceiver primitive control Table 2, refer Xilinx documentation.
0x0009	0x0024	GENERIC_INFO				Physical layer info
		[20]	QPLL_ENABLE	RO	0x00	Using QPLL.
		[19:16]	XCVR_TYPE[3:0]	RO	0x00	Xilinx encoded values.
		[13:12]	LINK_MODE	RO	0x00	Link layer mode : 01 - 8B10B decoder (aka 204B) 10 - 64B66B decoder (aka 204C); Available from version 17.3.a
		[8]	TX_OR_RX_N	RO	0x00	Transceiver type (transmit or receive)
		[7:0]	NUM_OF_LANES	RO	0x00	Physical layer number of lanes.
0x0010	0x0040	CM_SEL				Transceiver Access Register
		[7:0]	CM_SEL	RW	0x00	Transceiver common-DRP sel, set to 0xff for broadcast.
0x0011	0x0044	CM_CONTROL				Transceiver Access Register
		[28]	CM_WR	RW	0x00	Transceiver common-DRP sel, set to 0x1 for write, 0x0 for read.
		[27:16]	CM_ADDR	RW	0x00	Transceiver common-DRP read/write address.
		[15:0]	CM_WDATA	RW	0x00	Transceiver common-DRP write data.
0x0012	0x0048	CM_STATUS				Transceiver Access Register
		[16]	CM_BUSY	RO	0x00	Transceiver common-DRP access busy (0x1) or idle (0x0).
		[15:0]	CM_RDATA	RW	0x00	Transceiver common-DRP read data.
0x0018	0x0060	CH_SEL				Transceiver Access Register
		[7:0]	CH_SEL	RW	0x00	Transceiver channel-DRP sel, set to 0xff for broadcast.
0x0019	0x0064	CH_CONTROL				Transceiver Access Register
		[28]	CH_WR	RW	0x00	Transceiver channel-DRP sel, set to 0x1 for write, 0x0 for read.
		[27:16]	CH_ADDR	RW	0x00	Transceiver channel-DRP read/write address.
		[15:0]	CH_WDATA	RW	0x00	Transceiver channel-DRP write data.
0x001a	0x0068	CH_STATUS				Transceiver Access Register
		[16]	CH_BUSY	RO	0x00	Transceiver channel-DRP access busy (0x1) or idle (0x0).
		[15:0]	CH_RDATA	RW	0x00	Transceiver channel-DRP read data.
0x0020	0x0080	ES_SEL				Transceiver Access Register
		[7:0]	ES_SEL	RW	0x00	Transceiver eye-scan-DRP sel, set to 0xff for broadcast.
0x0028	0x00a0	ES_REQ				Transceiver eye-scan Request Register
		[0]	ES_REQ	RW	0x00	Transceiver eye-scan request, set this bit to initiate an eye-scan, this bit auto-clears when scan is complete.
0x0029	0x00a4	ES_CONTROL_1				Transceiver eye-scan Control Register
		[4:0]	ES_PRESCALE[4:0]	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
0x002a	0x00a8	0x00a8				ES_CONTROL_2 Transceiver eye-scan Control Register
		[25:24]	ES_VOFFSET_RANGE	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
		[23:16]	ES_VOFFSET_STEP	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
		[15:8]	ES_VOFFSET_MAX	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
		[7:0]	ES_VOFFSET_MIN	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
0x002b	0x00ac	ES_CONTROL_3				Transceiver eye-scan Control Register
		[27:16]	ES_HOFFSET_MAX	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
		[11:0]	ES_HOFFSET_MIN	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
0x002c	0x00b0	ES_CONTROL_4				Transceiver eye-scan Control Register
		[11:0]	ES_HOFFSET_STEP	RW	0x00	Transceiver eye-scan control, refer Xilinx documentation.
0x002d	0x00b4	ES_CONTROL_5				Transceiver eye-scan Control Register
		[31:0]	ES_STARTADDR	RW	0x00	Transceiver eye-scan control, DMA start address (ES data is written to this memory address).
0x002e	0x00b8	ES_STATUS				Transceiver eye-scan Status Register
		[0]	ES_STATUS	RO	0x00	If set, indicates an error in ES DMA.
0x002F	0x00bc	ES_RESET				Transceiver eye-scan reset control register
		[n]	ES_RESET	RW	0x00	Controls the EYESCANRESET pin of the GTH/GTY transceivers for lane n.
0x0030	0x00c0	TX_DIFFCTRL				Transceiver primitive control, refer Xilinx documentation.
		[31:0]	TX_DIFFCTRL	RW	0x00	TX driver swing control.
0x0031	0x00c4	TX_POSTCURSOR				Transceiver primitive control, refer Xilinx documentation.
		[31:0]	TX_POSTCURSOR	RW	0x00	Transmiter post-cursor TX pre-emphasis control.
0x0032	0x00c8	TX_PRECURSOR				Transceiver primitive control, refer Xilinx documentation.
		[31:0]	TX_PRECURSOR	RW	0x00	Transmiter pre-cursor TX pre-emphasis control.
0x0050	0x0140	FPGA_VOLTAGE				FPGA device voltage information
		[15:0]	FPGA_VOLTAGE	RO	0x00	The voltage of the FPGA device in mv
0x0060	0x0180	PRBS_CNTRL				Transceiver PRBS control
		[16]	PRBSFORCEERR	RW	0x00	Valid for TX. If set, a single error is forced in the PRBS transmitter for every clock cycle. Can be used to test the PRBS checkers on the other side of the link.
		[8]	PRBSCNTRESET	RW	0x00	Valid for RX. Resets the PRBS error counter from the transceiver. Does not self clears. Value of error counter must be accessed via DRP.
		[3:0]	PRBSSEL	RW	0x00	PRBS checker or generator test pattern control. All zeros will put the PRBS in bypass mode. For TX non-zero values will stop the normal dataflow from link layer and will inject a pattern instead. See transceiver guide for specific values.
0x0061	0x0184	PRBS_STATUS				RX Transceiver PRBS status
		[8]	PRBSERR	RO	0x00	This sticky status output indicates that PRBS errors have occurred. Value of error counter must be accessed via DRP.
		[0]	PRBSLOCKED	RO	0x00	Ignore this bit for GTX transceivers. For others: Indicates that the RX PRBS checker has been error free for 15 XCLK cycles after reset. Once asserted High, it does not deassert until reset of the RX pattern checker via PRBSCNTRESET
Tue Mar 14 10:17:59 2023

PWM Generator (axi_pwm_gen)

Click to expand regmap

0x0000	0x0000	REG_VERSION				Version and Scratch Registers
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:0]	VERSION[31:0]	RO	0x00020000	Version number. Unique to all cores.
0x0001	0x0004	REG_ID				Core ID
		[31:0]	ID[31:0]	RO	0x00000000	Instance identifier number.
0x0002	0x0008	REG_SCRATCH				Version and Scratch Registers
		[31:0]	SCRATCH[31:0]	RW	0x00000000	Scratch register.
0x0003	0x000c	REG_CORE_MAGIC				Identification number
		[31:0]	CORE_MAGIC[31:0]	RW	0x601A3471	Identification number.
0x0004	0x0010	REG_RSTN				Reset and load values
		[1]	LOAD_CONFIG	WO	0x0	Loads the new values written in the config registers.
		[0]	RESET	RW	0x0	Reset, default is (0x0).
0x0005	0x0014	REG_NB_PULSES				Number of pulses
		[31:0]	NB_PULSES	RO	0x0000	Number of configurable pulses.
0x0010	0x0040	REG_PULSE_X_PERIOD				Pulse x period
		[31:0]	PULSE_X_PERIOD[31:0] - base + 'h4 for each channel → e.g. CH3 period - 'h4C	RW	0x0000	Pulse x duration, defined in number of clock cycles.
0x0020	0x0080	REG_PULSE_X_WIDTH				Pulse x width
		[31:0]	PULSE_X_WIDTH[31:0] - base + 'h4 for each channel → e.g. CH3 width - 'h8C	RW	0x0000	Pulse x width (high time), defined in number of clock cycles.
0x0030	0x00C0	REG_PULSE_X_OFFSET				Pulse x offset
		[31:0]	PULSE_X_OFFSET[31:0] - base + 'h4 for each channel → e.g. CH3 offset - 'hCC	RW	0x0000	Pulse x offset, defined in number of clock cycles.

Analog Devices Wiki

Base (common to all cores)

ADC Common (axi_ad*)

ADAQ8092

AD4858

AD7606X_PI

ADC Channel (axi_ad*)

IO Delay Control (axi_ad*)

DAC Common (axi_ad)

DAC Channel (axi_ad*)

Generic TDD Control (axi_tdd)

Transceiver TDD Control (axi_ad*)

JESD TPL (up_tpl_common)

JESD204 RX (axi_jesd204_rx)

JESD204 TX (axi_jesd204_tx)

DMA Controller (axi_dmac)

Fan Controller (axi_fan_control)

System ID (axi_system_id)

Clock Generator (axi_clkgen)

Clock Monitor (axi_clock_monitor)

HDMI Transmit (axi_hdmi_tx)

HDMI Receive (axi_hdmi_rx)

General Purpose Registers (axi_gpreg)

SPI Engine (axi_spi_engine)

Xilinx XCVR (axi_xcvr) Regmap

PWM Generator (axi_pwm_gen)

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