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This version is outdated by a newer approved version.DiffThis version (06 May 2022 13:34) was approved by Ionut Podgoreanu.The Previously approved version (24 Feb 2022 14:56) is available.Diff

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Base (common to all cores)

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ADC Common (axi_ad*)

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ADC Channel (axi_ad*)

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IO Delay Control (axi_ad*)

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DAC Common (axi_ad)

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DAC Channel (axi_ad*)

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Transceiver TDD Control (axi_ad*)

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JESD TPL (up_tpl_common)

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JESD204 RX (axi_jesd204_rx)

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JESD204 TX (axi_jesd204_tx)

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DMA Controller (axi_dmac)

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Fan Controller (axi_fan_control)

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System ID (axi_system_id)

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Clock Generator (axi_clkgen)

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Clock Monitor (axi_clock_monitor)

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HDMI Transmit (axi_hdmi_tx)

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HDMI Receive (axi_hdmi_rx)

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General Purpose Registers (axi_gpreg)

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SPI Engine (axi_spi_engine)

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Xilinx XCVR (axi_xcvr) Regmap

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PWM Generator (axi_pwm_gen)

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resources/fpga/docs/hdl/regmap.1651836822.txt.gz · Last modified: 06 May 2022 13:33 by Ionut Podgoreanu