This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revisionLast revisionBoth sides next revision | ||
resources:fpga:docs:hdl:regmap [16 Feb 2022 14:33] – Andrei Dragomir | resources:fpga:docs:hdl:regmap [01 Feb 2024 11:52] – Add the DMA Scatter-Gather registers. Ionut Podgoreanu | ||
---|---|---|---|
Line 1: | Line 1: | ||
- | |||
- | |||
==== Base (common to all cores) ==== | ==== Base (common to all cores) ==== | ||
Line 25: | Line 23: | ||
|::: |::: |[9] |SCALECORRECTION_ONLY |RO |0x0 |If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance) | | |::: |::: |[9] |SCALECORRECTION_ONLY |RO |0x0 |If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance) | | ||
|::: |::: |[12] |EXT_SYNC |RO |0x0 |If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal. | | |::: |::: |[12] |EXT_SYNC |RO |0x0 |If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal. | | ||
+ | |::: |::: |[13] |RD_RAW_DATA |RO |0x0 |If set, the ADC has the capability to read raw data in register REG_CHAN_RAW_DATA from adc_channel. | | ||
^0x0004 ^0x0010 ^REG_PPS_IRQ_MASK ^^^^PPS Interrupt mask ^ | ^0x0004 ^0x0010 ^REG_PPS_IRQ_MASK ^^^^PPS Interrupt mask ^ | ||
| | |[0] |PPS_IRQ_MASK |RW |0x1 |Mask bit for the 1PPS receiver interrupt | | | | |[0] |PPS_IRQ_MASK |RW |0x1 |Mask bit for the 1PPS receiver interrupt | | ||
Line 32: | Line 31: | ||
|::: |::: |[15:8] |SPEED_GRADE |RO |0x0 |Encoded value describing the FPGA's speed-grade | | |::: |::: |[15:8] |SPEED_GRADE |RO |0x0 |Encoded value describing the FPGA's speed-grade | | ||
|::: |::: |[7:0] |DEV_PACKAGE |RO |0x0 |Encoded value describing the device package. The package might affect high-speed interfaces | | |::: |::: |[7:0] |DEV_PACKAGE |RO |0x0 |Encoded value describing the device package. The package might affect high-speed interfaces | | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 50: | Line 49: | ||
|::: |::: |[15] |SYMB_OP |RW |0x0 |Select symbol data format mode (0x1) | | |::: |::: |[15] |SYMB_OP |RW |0x0 |Select symbol data format mode (0x1) | | ||
|::: |::: |[14] |SYMB_8_16B |RW |0x0 |Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b) | | |::: |::: |[14] |SYMB_8_16B |RW |0x0 |Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b) | | ||
- | |::: |::: |[12:8] |NUM_LANES[4: | + | |::: |::: |[12:8] |NUM_LANES[4: |
|::: |::: |[3] |SYNC |RW |0x0 |Initialize synchronization between multiple ADCs | | |::: |::: |[3] |SYNC |RW |0x0 |Initialize synchronization between multiple ADCs | | ||
|::: |::: |[2] |R1_MODE |RW |0x0 |Select number of RF channels 1 (0x1) or 2 (0x0). | | |::: |::: |[2] |R1_MODE |RW |0x0 |Select number of RF channels 1 (0x1) or 2 (0x0). | | ||
Line 59: | Line 58: | ||
|::: |::: |[2] |EXT_SYNC_DISARM |RW |0x0 |Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. | | |::: |::: |[2] |EXT_SYNC_DISARM |RW |0x0 |Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. | | ||
|::: |::: |[8] |MANUAL_SYNC_REQUEST |RW |0x0 |Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. | | |::: |::: |[8] |MANUAL_SYNC_REQUEST |RW |0x0 |Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears. | | ||
+ | ^0x0013 ^0x004c ^REG_CNTRL_3 ^^^^ADC Interface Control & Status ^ | ||
+ | | | |[8] |CRC_EN |RW |0x0 |Setting this bit will enable the CRC generation. | | ||
+ | |::: |::: |[7:0] |CUSTOM_CONTROL |RW |0x00 |{{page>: | ||
^0x0015 ^0x0054 ^REG_CLK_FREQ ^^^^ADC Interface Control & Status ^ | ^0x0015 ^0x0054 ^REG_CLK_FREQ ^^^^ADC Interface Control & Status ^ | ||
| | |[31:0] |CLK_FREQ[31: | | | |[31:0] |CLK_FREQ[31: | ||
Line 64: | Line 66: | ||
| | |[31:0] |CLK_RATIO[31: | | | |[31:0] |CLK_RATIO[31: | ||
^0x0017 ^0x005c ^REG_STATUS ^^^^ADC Interface Control & Status ^ | ^0x0017 ^0x005c ^REG_STATUS ^^^^ADC Interface Control & Status ^ | ||
- | | | |[3] |PN_ERR |RO |0x0 |If set, indicates pn error in one or more channels. | | + | | | |[4] |ADC_CTRL_STATUS |RO |0x0 |If set, indicates that the device' |
+ | |::: |::: |[3] |PN_ERR |RO |0x0 |If set, indicates pn error in one or more channels. | | ||
|::: |::: |[2] |PN_OOS |RO |0x0 |If set, indicates pn oos in one or more channels. | | |::: |::: |[2] |PN_OOS |RO |0x0 |If set, indicates pn oos in one or more channels. | | ||
|::: |::: |[1] |OVER_RANGE |RO |0x0 |If set, indicates over range in one or more channels. | | |::: |::: |[1] |OVER_RANGE |RO |0x0 |If set, indicates over range in one or more channels. | | ||
Line 91: | Line 94: | ||
^0x001F ^0x007c ^REG_DRP_RDATA ^^^^ADC DRP Read Data ^ | ^0x001F ^0x007c ^REG_DRP_RDATA ^^^^ADC DRP Read Data ^ | ||
| | |[15:0] |DRP_RDATA[15: | | | |[15:0] |DRP_RDATA[15: | ||
+ | ^0x0020 ^0x0080 ^REG_ADC_CONFIG_WR ^^^^ADC Write Configuration Data ^ | ||
+ | | | |[31:0] |ADC_CONFIG_WR[31: | ||
+ | ^0x0021 ^0x0084 ^REG_ADC_CONFIG_RD ^^^^ADC Read Configuration Data ^ | ||
+ | | | |[31:0] |ADC_CONFIG_RD[31: | ||
^0x0022 ^0x0088 ^REG_UI_STATUS ^^^^User Interface Status ^ | ^0x0022 ^0x0088 ^REG_UI_STATUS ^^^^User Interface Status ^ | ||
| | |[2] |UI_OVF |RW1C |0x0 |User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. | | | | |[2] |UI_OVF |RW1C |0x0 |User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. | | ||
|::: |::: |[1] |UI_UNF |RW1C |0x0 |User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. | | |::: |::: |[1] |UI_UNF |RW1C |0x0 |User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. | | ||
|::: |::: |[0] |UI_RESERVED |RW1C |0x0 |Reserved for backward compatibility. | | |::: |::: |[0] |UI_RESERVED |RW1C |0x0 |Reserved for backward compatibility. | | ||
+ | ^0x0023 ^0x008c ^REG_ADC_CONFIG_CTRL ^^^^ADC RD/WR configuration ^ | ||
+ | | | |[31:0] |ADC_CONFIG_CTRL[31: | ||
^0x0028 ^0x00a0 ^REG_USR_CNTRL_1 ^^^^ADC Interface Control & Status ^ | ^0x0028 ^0x00a0 ^REG_USR_CNTRL_1 ^^^^ADC Interface Control & Status ^ | ||
| | |[7:0] |USR_CHANMAX[7: | | | |[7:0] |USR_CHANMAX[7: | ||
Line 107: | Line 116: | ||
^0x0031 ^0x00c4 ^REG_PPS_STATUS ^^^^PPS Status register ^ | ^0x0031 ^0x00c4 ^REG_PPS_STATUS ^^^^PPS Status register ^ | ||
| | |[0] |PPS_STATUS |RO |0x0 |If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it's not active. | | | | |[0] |PPS_STATUS |RO |0x0 |If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it's not active. | | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Fri Aug 11 18:29:53 2023 ^^^^^^ |
++++ | ++++ | ||
- | |||
==== ADC Channel (axi_ad*) ==== | ==== ADC Channel (axi_ad*) ==== | ||
Line 130: | Line 138: | ||
|::: |::: |[0] |ENABLE |RW |0x0 |If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected. | | |::: |::: |[0] |ENABLE |RW |0x0 |If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected. | | ||
^0x0101 ^0x0404 ^REG_CHAN_STATUS ^^^^ADC Interface Control & Status ^ | ^0x0101 ^0x0404 ^REG_CHAN_STATUS ^^^^ADC Interface Control & Status ^ | ||
- | | | |[2] |PN_ERR |RW1C |0x0 |PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared. | | + | | | |[12] |CRC_ERR |RW1C |0x0 |CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards. | |
+ | |::: |::: |[11:4] |STATUS_HEADER |RO |0x00 |The status header sent by the ADC.(compatible with AD7768/ | ||
+ | |::: |::: |[2] |PN_ERR |RW1C |0x0 |PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared. | | ||
|::: |::: |[1] |PN_OOS |RW1C |0x0 |PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern. | | |::: |::: |[1] |PN_OOS |RW1C |0x0 |PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern. | | ||
|::: |::: |[0] |OVER_RANGE |RW1C |0x0 |If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards. | | |::: |::: |[0] |OVER_RANGE |RW1C |0x0 |If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards. | | ||
+ | ^0x0102 ^0x0408 ^REG_CHAN_RAW_DATA ^^^^ADC Raw Data Reading ^ | ||
+ | | | |[31:0] |ADC_READ_DATA[31: | ||
^0x0104 ^0x0410 ^REG_CHAN_CNTRL_1 ^^^^ADC Interface Control & Status ^ | ^0x0104 ^0x0410 ^REG_CHAN_CNTRL_1 ^^^^ADC Interface Control & Status ^ | ||
| | |[31:16] |DCFILT_OFFSET[15: | | | |[31:16] |DCFILT_OFFSET[15: | ||
Line 154: | Line 166: | ||
^0x0120 ^0x0480 ^REG_* ^^^^Channel 2, similar to register 0x100 to 0x10f. ^ | ^0x0120 ^0x0480 ^REG_* ^^^^Channel 2, similar to register 0x100 to 0x10f. ^ | ||
^0x01F0 ^0x07c0 ^REG_* ^^^^Channel 15, similar to register 0x100 to 0x10f. ^ | ^0x01F0 ^0x07c0 ^REG_* ^^^^Channel 15, similar to register 0x100 to 0x10f. ^ | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 172: | Line 184: | ||
^0x0F ^0x003c ^REG_DELAY_CONTROL_F ^^^^Delay Control & Status ^ | ^0x0F ^0x003c ^REG_DELAY_CONTROL_F ^^^^Delay Control & Status ^ | ||
| | |[4:0] |DELAY_CONTROL_IO_F |RW |0x00 |Tap value for input/ | | | |[4:0] |DELAY_CONTROL_IO_F |RW |0x00 |Tap value for input/ | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 227: | Line 239: | ||
^0x001F ^0x007c ^REG_DRP_RDATA ^^^^DAC Interface Control & Status ^ | ^0x001F ^0x007c ^REG_DRP_RDATA ^^^^DAC Interface Control & Status ^ | ||
| | |[15:0] |DRP_RDATA |RO |0x0000 |DRP read data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). | | | | |[15:0] |DRP_RDATA |RO |0x0000 |DRP read data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). | | ||
+ | ^0x0020 ^0x0080 ^REG_DAC_CUSTOM_RD ^^^^DAC Read Configuration Data ^ | ||
+ | | | |[31:0] |DAC_CUSTOM_RD[31: | ||
+ | ^0x0021 ^0x0084 ^REG_DAC_CUSTOM_WR ^^^^DAC Write Configuration Data ^ | ||
+ | | | |[31:0] |DAC_CUSTOM_WR[31: | ||
^0x0022 ^0x0088 ^REG_UI_STATUS ^^^^User Interface Status ^ | ^0x0022 ^0x0088 ^REG_UI_STATUS ^^^^User Interface Status ^ | ||
- | | | |[1] |UI_OVF |RW1C |0x0 |User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. | | + | | | |[4] |IF_BUSY |RO |0x0 |Interface busy. If set, indicates that the data interface is busy. | |
+ | |::: |::: |[1] |UI_OVF |RW1C |0x0 |User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. | | ||
|::: |::: |[0] |UI_UNF |RW1C |0x0 |User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. | | |::: |::: |[0] |UI_UNF |RW1C |0x0 |User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit. | | ||
+ | ^0x0023 ^0x008c ^REG_DAC_CUSTOM_CTRL ^^^^DAC Control Configuration Data ^ | ||
+ | | | |[31:0] |DAC_CUSTOM_CTRL[31: | ||
^0x0028 ^0x00a0 ^REG_USR_CNTRL_1 ^^^^DAC User Control & Status ^ | ^0x0028 ^0x00a0 ^REG_USR_CNTRL_1 ^^^^DAC User Control & Status ^ | ||
| | |[7:0] |USR_CHANMAX[7: | | | |[7:0] |USR_CHANMAX[7: | ||
Line 236: | Line 255: | ||
^0x002F ^0x00bc ^REG_DAC_GPIO_OUT ^^^^DAC GPIO outputs ^ | ^0x002F ^0x00bc ^REG_DAC_GPIO_OUT ^^^^DAC GPIO outputs ^ | ||
| | |[31:0] |DAC_GPIO_OUT[31: | | | |[31:0] |DAC_GPIO_OUT[31: | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
+ | |||
+ | |||
Line 247: | Line 268: | ||
|DWORD |BYTE |::: |::: |::: |::: |::: | | |DWORD |BYTE |::: |::: |::: |::: |::: | | ||
^0x0100 ^0x0400 ^REG_CHAN_CNTRL_1 ^^^^DAC Channel Control & Status (channel - 0) ^ | ^0x0100 ^0x0400 ^REG_CHAN_CNTRL_1 ^^^^DAC Channel Control & Status (channel - 0) ^ | ||
- | | | |[15:0] |DDS_SCALE_1[15: | + | | | |[21:16] |DDS_PHASE_DW[5: |
+ | |::: |::: |[15:0] |DDS_SCALE_1[15: | ||
^0x0101 ^0x0404 ^REG_CHAN_CNTRL_2 ^^^^DAC Channel Control & Status (channel - 0) ^ | ^0x0101 ^0x0404 ^REG_CHAN_CNTRL_2 ^^^^DAC Channel Control & Status (channel - 0) ^ | ||
- | | | |[31:16] |DDS_INIT_1[15: | + | | | |[31:16] |DDS_INIT_1[15: |
- | |::: |::: |[15:0] |DDS_INCR_1[15: | + | |::: |::: |[15:0] |DDS_INCR_1[15: |
^0x0102 ^0x0408 ^REG_CHAN_CNTRL_3 ^^^^DAC Channel Control & Status (channel - 0) ^ | ^0x0102 ^0x0408 ^REG_CHAN_CNTRL_3 ^^^^DAC Channel Control & Status (channel - 0) ^ | ||
- | | | |[15:0] |DDS_SCALE_2[15: | + | | | |[15:0] |DDS_SCALE_2[15: |
^0x0103 ^0x040c ^REG_CHAN_CNTRL_4 ^^^^DAC Channel Control & Status (channel - 0) ^ | ^0x0103 ^0x040c ^REG_CHAN_CNTRL_4 ^^^^DAC Channel Control & Status (channel - 0) ^ | ||
- | | | |[31:16] |DDS_INIT_2[15: | + | | | |[31:16] |DDS_INIT_2[15: |
- | |::: |::: |[15:0] |DDS_INCR_2[15: | + | |::: |::: |[15:0] |DDS_INCR_2[15: |
^0x0104 ^0x0410 ^REG_CHAN_CNTRL_5 ^^^^DAC Channel Control & Status (channel - 0) ^ | ^0x0104 ^0x0410 ^REG_CHAN_CNTRL_5 ^^^^DAC Channel Control & Status (channel - 0) ^ | ||
| | |[31:16] |DDS_PATT_2[15: | | | |[31:16] |DDS_PATT_2[15: | ||
Line 275: | Line 297: | ||
|::: |::: |[7:0] |USR_DATATYPE_BITS[7: | |::: |::: |[7:0] |USR_DATATYPE_BITS[7: | ||
^0x0109 ^0x0424 ^REG_USR_CNTRL_4 ^^^^DAC Channel Control & Status (channel - 0) ^ | ^0x0109 ^0x0424 ^REG_USR_CNTRL_4 ^^^^DAC Channel Control & Status (channel - 0) ^ | ||
- | | | |[31:16] |USR_INTERPOLATION_M[15: | + | | | |[31:16] |USR_INTERPOLATION_M[15: |
|::: |::: |[15:0] |USR_INTERPOLATION_N[15: | |::: |::: |[15:0] |USR_INTERPOLATION_N[15: | ||
^0x010A ^0x0428 ^REG_USR_CNTRL_5 ^^^^DAC Channel Control & Status (channel - 0) ^ | ^0x010A ^0x0428 ^REG_USR_CNTRL_5 ^^^^DAC Channel Control & Status (channel - 0) ^ | ||
| | |[0] |DAC_IQ_MODE[0] |RW |0x0 |Enable complex mode. In this mode the driven data to the DAC must be a sequence | | | |[0] |DAC_IQ_MODE[0] |RW |0x0 |Enable complex mode. In this mode the driven data to the DAC must be a sequence | ||
- | |::: |::: |[1] |DAC_IQ_SWAP[1] |RW |0x0 |Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled. | | + | |::: |::: |[1] |DAC_IQ_SWAP[1] |RW |0x0 |Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled. | |
+ | ^0x010B ^0x042c ^REG_CHAN_CNTRL_9 ^^^^DAC Channel Control & Status (channel - 0) ^ | ||
+ | | | |[31:16] |DDS_INIT_1_EXTENDED[15: | ||
+ | |::: |::: |[15:0] |DDS_INCR_1_EXTENDED[15: | ||
+ | ^0x010C ^0x0430 ^REG_CHAN_CNTRL_10 ^^^^DAC Channel Control & Status (channel - 0) ^ | ||
+ | | | |[31:16] |DDS_INIT_2_EXTENDED[15: | ||
+ | |::: |::: |[15:0] |DDS_INCR_2_EXTENDED[15: | ||
^0x0110 ^0x0440 ^REG_* ^^^^Channel 1, similar to registers 0x100 to 0x10f. ^ | ^0x0110 ^0x0440 ^REG_* ^^^^Channel 1, similar to registers 0x100 to 0x10f. ^ | ||
^0x0120 ^0x0480 ^REG_* ^^^^Channel 2, similar to registers 0x100 to 0x10f. ^ | ^0x0120 ^0x0480 ^REG_* ^^^^Channel 2, similar to registers 0x100 to 0x10f. ^ | ||
^0x01F0 ^0x07c0 ^REG_* ^^^^Channel 15, similar to registers 0x100 to 0x10f. ^ | ^0x01F0 ^0x07c0 ^REG_* ^^^^Channel 15, similar to registers 0x100 to 0x10f. ^ | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Fri Sep 8 16:01:53 2023 ^^^^^^ |
+ | ++++ | ||
+ | |||
+ | |||
+ | ==== Generic TDD Control (axi_tdd) ==== | ||
+ | |||
+ | ++++ Click to expand regmap | | ||
+ | |< 100% 5% 5% 5% 25% 5% 5% 50% >| | ||
+ | |Address ||Bits |Name |Type |Default |Description | | ||
+ | |DWORD |BYTE |::: |::: |::: |::: |::: | | ||
+ | ^0x0000 ^0x0000 ^VERSION ^^^^Version of the peripheral. Follows semantic versioning. Current version 2.00.61. ^ | ||
+ | | | |[31:16] |VERSION_MAJOR |R |0x0002 | | | ||
+ | |::: |::: |[15:8] |VERSION_MINOR |R |0x00 | | | ||
+ | |::: |::: |[7:0] |VERSION_PATCH |R |0x61 | | | ||
+ | ^0x0001 ^0x0004 ^PERIPHERAL_ID ^^^^ ^ | ||
+ | | | |[31:0] |PERIPHERAL_ID |R |'' | ||
+ | ^0x0002 ^0x0008 ^SCRATCH ^^^^ ^ | ||
+ | | | |[31:0] |SCRATCH |RW |0x00000000 |Scratch register useful for debug. | | ||
+ | ^0x0003 ^0x000c ^IDENTIFICATION ^^^^ ^ | ||
+ | | | |[31:0] |IDENTIFICATION |R |0x5444444E |Peripheral identification (' | ||
+ | ^0x0004 ^0x0010 ^INTERFACE_DESCRIPTION ^^^^ ^ | ||
+ | | | |[30:24] |SYNC_COUNT_WIDTH |R |'' | ||
+ | |::: |::: |[21:16] |BURST_COUNT_WIDTH |R |'' | ||
+ | |::: |::: |[13:8] |REGISTER_WIDTH |R |'' | ||
+ | |::: |::: |[7] |SYNC_EXTERNAL_CDC |R |'' | ||
+ | |::: |::: |[6] |SYNC_EXTERNAL |R |'' | ||
+ | |::: |::: |[5] |SYNC_INTERNAL |R |'' | ||
+ | |::: |::: |[4:0] |CHANNEL_COUNT_EXTRA |R |'' | ||
+ | ^0x0005 ^0x0014 ^DEFAULT_POLARITY ^^^^ ^ | ||
+ | | | |[31:0] |DEFAULT_POLARITY |R |'' | ||
+ | ^0x0010 ^0x0040 ^CONTROL ^^^^TDD Control ^ | ||
+ | | | |[4] |SYNC_SOFT |RW |0x0 |Trigger the TDD core through a register write. This bit self clears. | | ||
+ | |::: |::: |[3] |SYNC_EXT |RW |0x0 |Enable external sync trigger. This bit is implemented if '' | ||
+ | |::: |::: |[2] |SYNC_INT |RW |0x0 |Enable internal sync trigger. This bit is implemented if '' | ||
+ | |::: |::: |[1] |SYNC_RST |RW |0x0 |Reset the internal counter while running when receiving a sync event | | ||
+ | |::: |::: |[0] |ENABLE |RW |0x0 |Module enable | | ||
+ | ^0x0011 ^0x0044 ^CHANNEL_ENABLE ^^^^TDD Channel Enable ^ | ||
+ | | | |[31:0] |CHANNEL_ENABLE |RW |0x00000000 |Enable bits per channel - LSB corresponds to CH0, MSB to CH31 | | ||
+ | ^0x0012 ^0x0048 ^CHANNEL_POLARITY ^^^^TDD Channel Polarity ^ | ||
+ | | | |[31:0] |CHANNEL_POLARITY |RW |0x00000000 |Polarity bits per channel - LSB corresponds to CH0, MSB to CH31 | | ||
+ | ^0x0013 ^0x004c ^BURST_COUNT ^^^^TDD Number of frames per burst ^ | ||
+ | | | |[31:0] |BURST_COUNT |RW |0x00000000 |If set to 0x0 and enabled - the controller operates in TDD mode as long as the ENABLE bit is set. If set to a non-zero value, the controller operates for the set number of frames and then stops. | | ||
+ | ^0x0014 ^0x0050 ^STARTUP_DELAY ^^^^TDD Transmission startup delay ^ | ||
+ | | | |[31:0] |STARTUP_DELAY |RW |0x00000000 |The initial delay value before the beginning of the first frame; defined in clock cycles. | | ||
+ | ^0x0015 ^0x0054 ^FRAME_LENGTH ^^^^TDD Frame length ^ | ||
+ | | | |[31:0] |FRAME_LENGTH |RW |0x00000000 |The length of the transmission frame; defined in clock cycles. | | ||
+ | ^0x0016 ^0x0058 ^SYNC_COUNTER_LOW ^^^^TDD Sync counter ^ | ||
+ | | | |[31:0] |SYNC_COUNTER_LOW |RW |0x00000000 |The LSB slice of the offset (from sync counter equal zero) when an internal sync pulse is generated. This register is implemented if '' | ||
+ | ^0x0017 ^0x005c ^SYNC_COUNTER_HIGH ^^^^TDD Sync counter ^ | ||
+ | | | |[31:0] |SYNC_COUNTER_HIGH |RW |0x00000000 |The MSB slice of the offset (from sync counter equal zero) when an internal sync pulse is generated. This register is implemented if '' | ||
+ | ^0x0018 ^0x0060 ^STATUS ^^^^Peripheral Status ^ | ||
+ | | | |[1:0] |STATE |R |0x0 |The current state of the peripheral FSM; used for debugging purposes. | | ||
+ | ^0x0020 ^0x0080 ^CH0_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH0_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH0 is set. | | ||
+ | ^0x0021 ^0x0084 ^CH0_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH0_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH0 is reset. | | ||
+ | ^0x0022 ^0x0088 ^CH1_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH1_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH1 is set. This register is implemented if '' | ||
+ | ^0x0023 ^0x008c ^CH1_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH1_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH1 is reset. This register is implemented if '' | ||
+ | ^0x0024 ^0x0090 ^CH2_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH2_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH2 is set. This register is implemented if '' | ||
+ | ^0x0025 ^0x0094 ^CH2_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH2_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH2 is reset. This register is implemented if '' | ||
+ | ^0x0026 ^0x0098 ^CH3_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH3_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH3 is set. This register is implemented if '' | ||
+ | ^0x0027 ^0x009c ^CH3_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH3_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH3 is reset. This register is implemented if '' | ||
+ | ^0x0028 ^0x00a0 ^CH4_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH4_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH4 is set. This register is implemented if '' | ||
+ | ^0x0029 ^0x00a4 ^CH4_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH4_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH4 is reset. This register is implemented if '' | ||
+ | ^0x002A ^0x00a8 ^CH5_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH5_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH5 is set. This register is implemented if '' | ||
+ | ^0x002B ^0x00ac ^CH5_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH5_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH5 is reset. This register is implemented if '' | ||
+ | ^0x002C ^0x00b0 ^CH6_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH6_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH6 is set. This register is implemented if '' | ||
+ | ^0x002D ^0x00b4 ^CH6_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH6_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH6 is reset. This register is implemented if '' | ||
+ | ^0x002E ^0x00b8 ^CH7_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH7_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH7 is set. This register is implemented if '' | ||
+ | ^0x002F ^0x00bc ^CH7_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH7_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH7 is reset. This register is implemented if '' | ||
+ | ^0x0030 ^0x00c0 ^CH8_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH8_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH8 is set. This register is implemented if '' | ||
+ | ^0x0031 ^0x00c4 ^CH8_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH8_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH8 is reset. This register is implemented if '' | ||
+ | ^0x0032 ^0x00c8 ^CH9_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH9_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH9 is set. This register is implemented if '' | ||
+ | ^0x0033 ^0x00cc ^CH9_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH9_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH9 is reset. This register is implemented if '' | ||
+ | ^0x0034 ^0x00d0 ^CH10_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH10_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH10 is set. This register is implemented if '' | ||
+ | ^0x0035 ^0x00d4 ^CH10_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH10_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH10 is reset. This register is implemented if '' | ||
+ | ^0x0036 ^0x00d8 ^CH11_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH11_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH11 is set. This register is implemented if '' | ||
+ | ^0x0037 ^0x00dc ^CH11_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH11_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH11 is reset. This register is implemented if '' | ||
+ | ^0x0038 ^0x00e0 ^CH12_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH12_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH12 is set. This register is implemented if '' | ||
+ | ^0x0039 ^0x00e4 ^CH12_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH12_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH12 is reset. This register is implemented if '' | ||
+ | ^0x003A ^0x00e8 ^CH13_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH13_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH13 is set. This register is implemented if '' | ||
+ | ^0x003B ^0x00ec ^CH13_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH13_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH13 is reset. This register is implemented if '' | ||
+ | ^0x003C ^0x00f0 ^CH14_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH14_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH14 is set. This register is implemented if '' | ||
+ | ^0x003D ^0x00f4 ^CH14_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH14_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH14 is reset. This register is implemented if '' | ||
+ | ^0x003E ^0x00f8 ^CH15_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH15_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH15 is set. This register is implemented if '' | ||
+ | ^0x003F ^0x00fc ^CH15_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH15_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH15 is reset. This register is implemented if '' | ||
+ | ^0x0040 ^0x0100 ^CH16_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH16_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH16 is set. This register is implemented if '' | ||
+ | ^0x0041 ^0x0104 ^CH16_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH16_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH16 is reset. This register is implemented if '' | ||
+ | ^0x0042 ^0x0108 ^CH17_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH17_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH17 is set. This register is implemented if '' | ||
+ | ^0x0043 ^0x010c ^CH17_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH17_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH17 is reset. This register is implemented if '' | ||
+ | ^0x0044 ^0x0110 ^CH18_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH18_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH18 is set. This register is implemented if '' | ||
+ | ^0x0045 ^0x0114 ^CH18_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH18_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH18 is reset. This register is implemented if '' | ||
+ | ^0x0046 ^0x0118 ^CH19_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH19_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH19 is set. This register is implemented if '' | ||
+ | ^0x0047 ^0x011c ^CH19_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH19_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH19 is reset. This register is implemented if '' | ||
+ | ^0x0048 ^0x0120 ^CH20_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH20_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH20 is set. This register is implemented if '' | ||
+ | ^0x0049 ^0x0124 ^CH20_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH20_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH20 is reset. This register is implemented if '' | ||
+ | ^0x004A ^0x0128 ^CH21_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH21_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH21 is set. This register is implemented if '' | ||
+ | ^0x004B ^0x012c ^CH21_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH21_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH21 is reset. This register is implemented if '' | ||
+ | ^0x004C ^0x0130 ^CH22_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH22_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH22 is set. This register is implemented if '' | ||
+ | ^0x004D ^0x0134 ^CH22_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH22_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH22 is reset. This register is implemented if '' | ||
+ | ^0x004E ^0x0138 ^CH23_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH23_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH23 is set. This register is implemented if '' | ||
+ | ^0x004F ^0x013c ^CH23_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH23_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH23 is reset. This register is implemented if '' | ||
+ | ^0x0050 ^0x0140 ^CH24_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH24_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH24 is set. This register is implemented if '' | ||
+ | ^0x0051 ^0x0144 ^CH24_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH24_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH24 is reset. This register is implemented if '' | ||
+ | ^0x0052 ^0x0148 ^CH25_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH25_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH25 is set. This register is implemented if '' | ||
+ | ^0x0053 ^0x014c ^CH25_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH25_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH25 is reset. This register is implemented if '' | ||
+ | ^0x0054 ^0x0150 ^CH26_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH26_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH26 is set. This register is implemented if '' | ||
+ | ^0x0055 ^0x0154 ^CH26_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH26_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH26 is reset. This register is implemented if '' | ||
+ | ^0x0056 ^0x0158 ^CH27_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH27_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH27 is set. This register is implemented if '' | ||
+ | ^0x0057 ^0x015c ^CH27_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH27_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH27 is reset. This register is implemented if '' | ||
+ | ^0x0058 ^0x0160 ^CH28_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH28_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH28 is set. This register is implemented if '' | ||
+ | ^0x0059 ^0x0164 ^CH28_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH28_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH28 is reset. This register is implemented if '' | ||
+ | ^0x005A ^0x0168 ^CH29_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH29_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH29 is set. This register is implemented if '' | ||
+ | ^0x005B ^0x016c ^CH29_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH29_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH29 is reset. This register is implemented if '' | ||
+ | ^0x005C ^0x0170 ^CH30_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH30_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH30 is set. This register is implemented if '' | ||
+ | ^0x005D ^0x0174 ^CH30_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH30_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH30 is reset. This register is implemented if '' | ||
+ | ^0x005E ^0x0178 ^CH31_ON ^^^^Channel Set ^ | ||
+ | | | |[31:0] |CH31_ON |RW |0x00000000 |The offset (from frame count equal zero), when CH31 is set. This register is implemented if '' | ||
+ | ^0x005F ^0x017c ^CH31_OFF ^^^^Channel Reset ^ | ||
+ | | | |[31:0] |CH31_OFF |RW |0x00000000 |The offset (from frame count equal zero), when CH31 is reset. This register is implemented if '' | ||
+ | ^Tue Mar 14 10:17:59 2023 ^^^^^^ | ||
++++ | ++++ | ||
Line 359: | Line 567: | ||
^0x003B ^0x00ec ^REG_TDD_TX_DP_OFF_2 ^^^^TDD Control & Status ^ | ^0x003B ^0x00ec ^REG_TDD_TX_DP_OFF_2 ^^^^TDD Control & Status ^ | ||
| | |[23:0] |TDD_TX_DP_OFF_2 |RW |0x000000 |The secondary pointer for TX_DP_OFF. | | | | |[23:0] |TDD_TX_DP_OFF_2 |RW |0x000000 |The secondary pointer for TX_DP_OFF. | | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 383: | Line 591: | ||
^0x00092 ^0x0248 ^REG_* ^^^^Profile 1, similar to registers 0x00010 to 0x00011. ^ | ^0x00092 ^0x0248 ^REG_* ^^^^Profile 1, similar to registers 0x00010 to 0x00011. ^ | ||
^0x00094 ^0x0250 ^REG_* ^^^^Profile 2, similar to registers 0x00010 to 0x00011. ^ | ^0x00094 ^0x0250 ^REG_* ^^^^Profile 2, similar to registers 0x00010 to 0x00011. ^ | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 504: | Line 712: | ||
^0xc5 + 0x08*n ^0x0314 +0x20*n ^LANEn_ILAS1 ^^^^Received ILAS config data for the n-th lane. ^ | ^0xc5 + 0x08*n ^0x0314 +0x20*n ^LANEn_ILAS1 ^^^^Received ILAS config data for the n-th lane. ^ | ||
| | |[31:29] |Reserved |RO |0x00 | | | | | |[31:29] |Reserved |RO |0x00 | | | ||
- | |::: |::: |[28:24] |K |RO |0x00 |K (Frames per multi-frame) field of the ILAS config sequence. | | + | |::: |::: |[28:24] |K |RO |0x00 |K (Frames per multi-frame) field of the ILAS config sequence |
- | |::: |::: |[23:16] |F |RO |0x00 |F (Octets per frame) field of the ILAS config sequence. | | + | |::: |::: |[23:16] |F |RO |0x00 |F (Octets per frame) field of the ILAS config sequence |
|::: |::: |[15] |SCR |RO |0x0 |SCR (Scrambling enabled) field of the ILAS config sequence. | | |::: |::: |[15] |SCR |RO |0x0 |SCR (Scrambling enabled) field of the ILAS config sequence. | | ||
|::: |::: |[14:13] |Reserved |RO |0x0 | | | |::: |::: |[14:13] |Reserved |RO |0x0 | | | ||
- | |::: |::: |[12:8] |L |RO |0x00 |L (Number of lanes) field of the ILAS config sequence. | | + | |::: |::: |[12:8] |L |RO |0x00 |L (Number of lanes) field of the ILAS config sequence |
|::: |::: |[7:5] |Reserved |RO |0x0 | | | |::: |::: |[7:5] |Reserved |RO |0x0 | | | ||
|::: |::: |[4:0] |LID |RO |0x00 |LID (Lane ID) field of the ILAS config sequence. | | |::: |::: |[4:0] |LID |RO |0x00 |LID (Lane ID) field of the ILAS config sequence. | | ||
^0xc6 + 0x08*n ^0x0318 +0x20*n ^LANEn_ILAS2 ^^^^Received ILAS config data for the n-th lane. ^ | ^0xc6 + 0x08*n ^0x0318 +0x20*n ^LANEn_ILAS2 ^^^^Received ILAS config data for the n-th lane. ^ | ||
| | |[31:29] |JESDV |RO |0x0 |JESDV (JESD204 version) field of the ILAS config sequence. | | | | |[31:29] |JESDV |RO |0x0 |JESDV (JESD204 version) field of the ILAS config sequence. | | ||
- | |::: |::: |[28:24] |S |RO |0x00 |S (Samples per frame) field of the ILAS config sequence. | | + | |::: |::: |[28:24] |S |RO |0x00 |S (Samples per frame) field of the ILAS config sequence |
|::: |::: |[23:21] |SUBCLASSV |RO |0x0 |SUBCLASSV (JESD204B subclass) field of the ILAS config sequence. | | |::: |::: |[23:21] |SUBCLASSV |RO |0x0 |SUBCLASSV (JESD204B subclass) field of the ILAS config sequence. | | ||
- | |::: |::: |[20:16] |NP |RO |0x00 |N' (Total number of bits per sample) field of the ILAS config sequence. | | + | |::: |::: |[20:16] |NP |RO |0x00 |N' (Total number of bits per sample) field of the ILAS config sequence |
|::: |::: |[15:14] |CS |RO |0x0 |CS (Control bits per sample) field of the ILAS config sequence. | | |::: |::: |[15:14] |CS |RO |0x0 |CS (Control bits per sample) field of the ILAS config sequence. | | ||
|::: |::: |[13] |Reserved |RO |0x0 | | | |::: |::: |[13] |Reserved |RO |0x0 | | | ||
- | |::: |::: |[12:8] |N |RO |0x00 |N (Converter resolution) field of the ILAS config sequence. | | + | |::: |::: |[12:8] |N |RO |0x00 |N (Converter resolution) field of the ILAS config sequence |
- | |::: |::: |[7:0] |M |RO |0x00 |M (Number of converters) field of the ILAS config sequence. | | + | |::: |::: |[7:0] |M |RO |0x00 |M (Number of converters) field of the ILAS config sequence |
^0xc7 + 0x08*n ^0x031c +0x20*n ^LANEn_ILAS3 ^^^^Received ILAS config data for the n-th lane. ^ | ^0xc7 + 0x08*n ^0x031c +0x20*n ^LANEn_ILAS3 ^^^^Received ILAS config data for the n-th lane. ^ | ||
| | |[31:24] |FCHK |RO |0x00 |FCHK (Checksum) field of the ILAS config sequence. | | | | |[31:24] |FCHK |RO |0x00 |FCHK (Checksum) field of the ILAS config sequence. | | ||
Line 526: | Line 734: | ||
|::: |::: |[6:5] |Reserved |RO |0x0 | | | |::: |::: |[6:5] |Reserved |RO |0x0 | | | ||
|::: |::: |[4:0] |CF |RO |0x00 |CF (control words per frame) field of the ILAS config sequence | | |::: |::: |[4:0] |CF |RO |0x00 |CF (control words per frame) field of the ILAS config sequence | | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 625: | Line 833: | ||
^0xc5 + 0x08*n ^0x0314 +0x20*n ^LANEn_ILAS1 ^^^^ILAS config data for the n-th lane. Valid for 8B/10B link. ^ | ^0xc5 + 0x08*n ^0x0314 +0x20*n ^LANEn_ILAS1 ^^^^ILAS config data for the n-th lane. Valid for 8B/10B link. ^ | ||
| | |[31:29] |Reserved |RO |0x00 | | | | | |[31:29] |Reserved |RO |0x00 | | | ||
- | |::: |::: |[28:24] |K |RW |0x00 |K (Frames per multi-frame) field of the ILAS config sequence. | | + | |::: |::: |[28:24] |K |RW |0x00 |K (Frames per multi-frame) field of the ILAS config sequence |
- | |::: |::: |[23:16] |F |RW |0x00 |F (Octets per frame) field of the ILAS config sequence. | | + | |::: |::: |[23:16] |F |RW |0x00 |F (Octets per frame) field of the ILAS config sequence |
|::: |::: |[15] |SCR |RW |0x0 |SCR (Scrambling enabled) field of the ILAS config sequence. | | |::: |::: |[15] |SCR |RW |0x0 |SCR (Scrambling enabled) field of the ILAS config sequence. | | ||
|::: |::: |[14:13] |Reserved |RO |0x0 | | | |::: |::: |[14:13] |Reserved |RO |0x0 | | | ||
- | |::: |::: |[12:8] |L |RW |0x00 |L (Number of lanes) field of the ILAS config sequence. | | + | |::: |::: |[12:8] |L |RW |0x00 |L (Number of lanes) field of the ILAS config sequence |
|::: |::: |[7:5] |Reserved |RO |0x0 | | | |::: |::: |[7:5] |Reserved |RO |0x0 | | | ||
|::: |::: |[4:0] |LID |RW |0x00 |LID (Lane ID) field of the ILAS config sequence. | | |::: |::: |[4:0] |LID |RW |0x00 |LID (Lane ID) field of the ILAS config sequence. | | ||
^0xc6 + 0x08*n ^0x0318 +0x20*n ^LANEn_ILAS2 ^^^^ILAS config data for the n-th lane. Valid for 8B/10B link. ^ | ^0xc6 + 0x08*n ^0x0318 +0x20*n ^LANEn_ILAS2 ^^^^ILAS config data for the n-th lane. Valid for 8B/10B link. ^ | ||
| | |[31:29] |JESDV |RW |0x0 |JESDV (JESD204 version) field of the ILAS config sequence. | | | | |[31:29] |JESDV |RW |0x0 |JESDV (JESD204 version) field of the ILAS config sequence. | | ||
- | |::: |::: |[28:24] |S |RW |0x00 |S (Samples per frame) field of the ILAS config sequence. | | + | |::: |::: |[28:24] |S |RW |0x00 |S (Samples per frame) field of the ILAS config sequence |
|::: |::: |[23:21] |SUBCLASSV |RW |0x0 |SUBCLASSV (JESD204B subclass) field of the ILAS config sequence. | | |::: |::: |[23:21] |SUBCLASSV |RW |0x0 |SUBCLASSV (JESD204B subclass) field of the ILAS config sequence. | | ||
- | |::: |::: |[20:16] |NP |RW |0x00 |N' (Total number of bits per sample) field of the ILAS config sequence. | | + | |::: |::: |[20:16] |NP |RW |0x00 |N' (Total number of bits per sample) field of the ILAS config sequence |
|::: |::: |[15:14] |CS |RW |0x0 |CS (Control bits per sample) field of the ILAS config sequence. | | |::: |::: |[15:14] |CS |RW |0x0 |CS (Control bits per sample) field of the ILAS config sequence. | | ||
|::: |::: |[13] |Reserved |RO |0x0 | | | |::: |::: |[13] |Reserved |RO |0x0 | | | ||
- | |::: |::: |[12:8] |N |RW |0x00 |N (Converter resolution) field of the ILAS config sequence. | | + | |::: |::: |[12:8] |N |RW |0x00 |N (Converter resolution) field of the ILAS config sequence |
- | |::: |::: |[7:0] |M |RW |0x00 |M (Number of converters) field of the ILAS config sequence. | | + | |::: |::: |[7:0] |M |RW |0x00 |M (Number of converters) field of the ILAS config sequence |
^0xc7 + 0x08*n ^0x031c +0x20*n ^LANEn_ILAS3 ^^^^ILAS config data for the n-th lane. Valid for 8B/10B link. ^ | ^0xc7 + 0x08*n ^0x031c +0x20*n ^LANEn_ILAS3 ^^^^ILAS config data for the n-th lane. Valid for 8B/10B link. ^ | ||
| | |[31:24] |FCHK |RW |0x00 |FCHK (Checksum) field of the ILAS config sequence. | | | | |[31:24] |FCHK |RW |0x00 |FCHK (Checksum) field of the ILAS config sequence. | | ||
Line 647: | Line 855: | ||
|::: |::: |[6:5] |Reserved |RO |0x0 | | | |::: |::: |[6:5] |Reserved |RO |0x0 | | | ||
|::: |::: |[4:0] |CF |RO |0x00 |CF (control words per frame) field of the ILAS config sequence | | |::: |::: |[4:0] |CF |RO |0x00 |CF (control words per frame) field of the ILAS config sequence | | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 657: | Line 865: | ||
|Address ||Bits |Name |Type |Default |Description | | |Address ||Bits |Name |Type |Default |Description | | ||
|DWORD |BYTE |::: |::: |::: |::: |::: | | |DWORD |BYTE |::: |::: |::: |::: |::: | | ||
- | ^0x000 ^0x0000 ^VERSION ^^^^Version of the peripheral. Follows semantic versioning. Current version 4.03.61. ^ | + | ^0x000 ^0x0000 ^VERSION ^^^^Version of the peripheral. Follows semantic versioning. Current version 4.05.61. ^ |
| | |[31:16] |VERSION_MAJOR |RO |0x04 | | | | | |[31:16] |VERSION_MAJOR |RO |0x04 | | | ||
- | |::: |::: |[15:8] |VERSION_MINOR |RO |0x03 | | | + | |::: |::: |[15:8] |VERSION_MINOR |RO |0x05 | | |
|::: |::: |[7:0] |VERSION_PATCH |RO |0x61 | | | |::: |::: |[7:0] |VERSION_PATCH |RO |0x61 | | | ||
^0x001 ^0x0004 ^PERIPHERAL_ID ^^^^ ^ | ^0x001 ^0x0004 ^PERIPHERAL_ID ^^^^ ^ | ||
Line 672: | Line 880: | ||
|::: |::: |[11:8] |BYTES_PER_BEAT_SRC_LOG2 |R |log2('' | |::: |::: |[11:8] |BYTES_PER_BEAT_SRC_LOG2 |R |log2('' | ||
|::: |::: |[13:12] |DMA_TYPE_SRC |R |'' | |::: |::: |[13:12] |DMA_TYPE_SRC |R |'' | ||
+ | |::: |::: |[19:16] |BYTES_PER_BURST_WIDTH |R |'' | ||
^0x020 ^0x0080 ^IRQ_MASK ^^^^ ^ | ^0x020 ^0x0080 ^IRQ_MASK ^^^^ ^ | ||
| | |[1] |TRANSFER_COMPLETED |RW |0x1 |Masks the TRANSFER_COMPLETED IRQ. | | | | |[1] |TRANSFER_COMPLETED |RW |0x1 |Masks the TRANSFER_COMPLETED IRQ. | | ||
Line 682: | Line 891: | ||
|::: |::: |[0] |TRANSFER_QUEUED |RO |0x0 |This bit will be asserted if a transfer has been queued and it is possible to queue the next transfer. Cleared together with the corresponding IRQ_PENDING bit. | | |::: |::: |[0] |TRANSFER_QUEUED |RO |0x0 |This bit will be asserted if a transfer has been queued and it is possible to queue the next transfer. Cleared together with the corresponding IRQ_PENDING bit. | | ||
^0x100 ^0x0400 ^CONTROL ^^^^ ^ | ^0x100 ^0x0400 ^CONTROL ^^^^ ^ | ||
- | | | |[1] |PAUSE |RW |0x0 |When set to 1 the currently active transfer is paused. It will be resumed once the bit is cleared again. | | + | | | |[2] |HWDESC |RW |0x0 |When set to 1 the scatter-gather transfers are enabled. |
+ | |::: |::: |[1] |PAUSE |RW |0x0 |When set to 1 the currently active transfer is paused. It will be resumed once the bit is cleared again. | | ||
|::: |::: |[0] |ENABLE |RW |0x0 |When set to 1 the DMA channel is enabled. | | |::: |::: |[0] |ENABLE |RW |0x0 |When set to 1 the DMA channel is enabled. | | ||
^0x101 ^0x0404 ^TRANSFER_ID ^^^^ ^ | ^0x101 ^0x0404 ^TRANSFER_ID ^^^^ ^ | ||
| | |[1:0] |TRANSFER_ID |RO |0x00 |This register contains the ID of the next transfer. The ID is generated by the DMAC and after the transfer has been started can be used to check if the transfer has finished by checking the corresponding bit in the TRANSFER_DONE register. The contents of this register is only valid if TRANSFER_SUBMIT is 0. | | | | |[1:0] |TRANSFER_ID |RO |0x00 |This register contains the ID of the next transfer. The ID is generated by the DMAC and after the transfer has been started can be used to check if the transfer has finished by checking the corresponding bit in the TRANSFER_DONE register. The contents of this register is only valid if TRANSFER_SUBMIT is 0. | | ||
^0x102 ^0x0408 ^TRANSFER_SUBMIT ^^^^ ^ | ^0x102 ^0x0408 ^TRANSFER_SUBMIT ^^^^ ^ | ||
- | | | |[0] |TRANSFER_SUBMIT |RW |0x00 |Writing a 1 to this register queues a new transfer. The bit transitions back to 0 once the transfer has been queued or the DMA channel is disabled. | + | | | |[0] |TRANSFER_SUBMIT |RW |0x0 |Writing a 1 to this register queues a new transfer. The bit transitions back to 0 once the transfer has been queued or the DMA channel is disabled. |
^0x103 ^0x040c ^FLAGS ^^^^ ^ | ^0x103 ^0x040c ^FLAGS ^^^^ ^ | ||
| | |[0] |CYCLIC |RW |'' | | | |[0] |CYCLIC |RW |'' | ||
Line 713: | Line 923: | ||
| | |[4:0] |ACTIVE_TRANSFER_ID |RO |0x00 |ID of the currently active transfer. When no transfer is active this register will be equal to the TRANSFER_ID register. | | | | |[4:0] |ACTIVE_TRANSFER_ID |RO |0x00 |ID of the currently active transfer. When no transfer is active this register will be equal to the TRANSFER_ID register. | | ||
^0x10c ^0x0430 ^STATUS ^^^^ ^ | ^0x10c ^0x0430 ^STATUS ^^^^ ^ | ||
- | | | |[31:0] |RESERVED |RO |0x00 |This register is reserved for future usage. Reading it will always return 0. | | + | | | |[31:0] |RESERVED |RO |0x00000000 |
^0x10d ^0x0434 ^CURRENT_DEST_ADDRESS ^^^^ ^ | ^0x10d ^0x0434 ^CURRENT_DEST_ADDRESS ^^^^ ^ | ||
- | | | |[31:0] |CURRENT_DEST_ADDRESS |RO |0x00 |Address to which the next data sample is written to. This register is only valid if the DMA channel has been configured for write to memory support. | | + | | | |[31:0] |CURRENT_DEST_ADDRESS |RO |0x00000000 |
^0x10e ^0x0438 ^CURRENT_SRC_ADDRESS ^^^^ ^ | ^0x10e ^0x0438 ^CURRENT_SRC_ADDRESS ^^^^ ^ | ||
- | | | |[31:0] |CURRENT_SRC_ADDRESS |RO |0x00 |Address form which the next data sample is read. This register is only valid if the DMA channel has been configured for read from memory support. | | + | | | |[31:0] |CURRENT_SRC_ADDRESS |RO |0x00000000 |
^0x112 ^0x0448 ^TRANSFER_PROGRESS ^^^^ ^ | ^0x112 ^0x0448 ^TRANSFER_PROGRESS ^^^^ ^ | ||
| | |[23:0] |TRANSFER_PROGRESS |RO |0x000000 |This field presents the number of bytes transferred to the destination for the current transfer. This register will be cleared once the transfer completes. This should be used for debugging purposes only. | | | | |[23:0] |TRANSFER_PROGRESS |RO |0x000000 |This field presents the number of bytes transferred to the destination for the current transfer. This register will be cleared once the transfer completes. This should be used for debugging purposes only. | | ||
^0x113 ^0x044c ^PARTIAL_TRANSFER_LENGTH ^^^^ ^ | ^0x113 ^0x044c ^PARTIAL_TRANSFER_LENGTH ^^^^ ^ | ||
- | | | |[31:0] |PARTIAL_LENGTH |RO |0x000000 | + | | | |[31:0] |PARTIAL_LENGTH |RO |0x00000000 |
^0x114 ^0x0450 ^PARTIAL_TRANSFER_ID ^^^^Must be read after the PARTIAL_TRANSFER_LENGTH registers. ^ | ^0x114 ^0x0450 ^PARTIAL_TRANSFER_ID ^^^^Must be read after the PARTIAL_TRANSFER_LENGTH registers. ^ | ||
| | |[1:0] |PARTIAL_TRANSFER_ID |RO |0x0 |ID of the transfer that was partial. | | | |[1:0] |PARTIAL_TRANSFER_ID |RO |0x0 |ID of the transfer that was partial. | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^0x115 ^0x0454 ^DESCRIPTOR_ID ^^^^ ^ |
+ | | | |[31:0] |DESCRIPTOR_ID |RO |0x00000000 |ID of the descriptor that points to the current memory segment being transferred. If HWDESC is set to 0, then this register returns 0. | | ||
+ | ^0x11f ^0x047c ^SG_ADDRESS ^^^^ ^ | ||
+ | | | |[31:0] |SG_ADDRESS |RW |0x00000000 |This register contains the starting address of the scatter-gather transfer. The address needs to be aligned to the bus width. | ||
+ | ^0x124 ^0x0490 ^DEST_ADDRESS_HIGH ^^^^ ^ | ||
+ | | | |[31:0] |DEST_ADDRESS_HIGH |RW |0x00000000 |This register contains the HIGH segment of the destination address of the transfer. | ||
+ | ^0x125 ^0x0494 ^SRC_ADDRESS_HIGH ^^^^ ^ | ||
+ | | | |[31:0] |SRC_ADDRESS_HIGH |RW |0x00000000 |This register contains the HIGH segment of the source address of the transfer. | ||
+ | ^0x126 ^0x0498 ^CURRENT_DEST_ADDRESS_HIGH ^^^^ ^ | ||
+ | | | |[31:0] |CURRENT_DEST_ADDRESS_HIGH |RO |0x00000000 |HIGH segment of the address to which the next data sample is written to. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for write to memory support. | | ||
+ | ^0x127 ^0x049c ^CURRENT_SRC_ADDRESS_HIGH ^^^^ ^ | ||
+ | | | |[31:0] |CURRENT_SRC_ADDRESS_HIGH |RO |0x00000000 |HIGH segment of the address from which the next data sample is read. This register is only valid if the DMA_AXI_ADDR_WIDTH is bigger than 32 and if the DMA channel has been configured for read from memory support. | | ||
+ | ^0x12f ^0x04bc ^SG_ADDRESS_HIGH ^^^^ ^ | ||
+ | | | |[31:0] |SG_ADDRESS_HIGH |RW |0x00000000 |HIGH segment of the starting address of the scatter-gather transfer. | ||
+ | ^Thu Feb 1 12:18:03 2024 ^^^^^^ | ||
++++ | ++++ | ||
Line 807: | Line 1031: | ||
^0x57 ^0x015c ^TACHO_100_TOL ^^^^ ^ | ^0x57 ^0x015c ^TACHO_100_TOL ^^^^ ^ | ||
| | |[31:0] |TACHO_100_TOL |RW |'' | | | |[31:0] |TACHO_100_TOL |RW |'' | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 831: | Line 1055: | ||
^0x400 ^0x1000 ^PRROM_START ^^^^ ^ | ^0x400 ^0x1000 ^PRROM_START ^^^^ ^ | ||
| | |[31:0] |SYSROM_START |RO |'' | | | |[31:0] |SYSROM_START |RO |'' | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 858: | Line 1082: | ||
^0x0050 ^0x0140 ^REG_FPGA_VOLTAGE ^^^^FPGA device voltage information ^ | ^0x0050 ^0x0140 ^REG_FPGA_VOLTAGE ^^^^FPGA device voltage information ^ | ||
| | |[15:0] |FPGA_VOLTAGE |RO |0x0 |The voltage of the FPGA device in mv | | | | |[15:0] |FPGA_VOLTAGE |RO |0x0 |The voltage of the FPGA device in mv | | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 908: | Line 1132: | ||
^0x001F ^0x007c ^CLOCK_15 ^^^^Measured clock_15 ^ | ^0x001F ^0x007c ^CLOCK_15 ^^^^Measured clock_15 ^ | ||
| | |[31:0] |clock_15 |RO |0x00000000 |Measured frequency of clock_15 | | | | |[31:0] |clock_15 |RO |0x00000000 |Measured frequency of clock_15 | | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 964: | Line 1188: | ||
| | |[31:16] |V_ENABLE_MAX[15: | | | |[31:16] |V_ENABLE_MAX[15: | ||
|::: |::: |[15:0] |V_ENABLE_MIN[15: | |::: |::: |[15:0] |V_ENABLE_MIN[15: | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 1001: | Line 1225: | ||
| | |[31:16] |VS_COUNT[15: | | | |[31:16] |VS_COUNT[15: | ||
|::: |::: |[15:0] |HS_COUNT[15: | |::: |::: |[15:0] |HS_COUNT[15: | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 1027: | Line 1251: | ||
^0x0220 ^0x0880 ^REG_* ^^^^Channel 2, similar to register 0x200 to 0x20f. ^ | ^0x0220 ^0x0880 ^REG_* ^^^^Channel 2, similar to register 0x200 to 0x20f. ^ | ||
^0x02f0 ^0x0bc0 ^REG_* ^^^^Channel 15, similar to register 0x200 to 0x20f. ^ | ^0x02f0 ^0x0bc0 ^REG_* ^^^^Channel 15, similar to register 0x200 to 0x20f. ^ | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 1084: | Line 1308: | ||
^0x45 ^0x0114 ^OFFLOAD0_SDO_FIFO ^^^^ ^ | ^0x45 ^0x0114 ^OFFLOAD0_SDO_FIFO ^^^^ ^ | ||
| | |[31:0] |OFFLOAD0_SDO_FIFO |WO |0x???????? |Offload SDO FIFO register. Writing to this register inserts an entry into the offload SDO FIFO. Writing to this register when the SDO FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000. | | | | |[31:0] |OFFLOAD0_SDO_FIFO |WO |0x???????? |Offload SDO FIFO register. Writing to this register inserts an entry into the offload SDO FIFO. Writing to this register when the SDO FIFO is full has no effect and the written entry is discarded. Reading from this register always returns 0x00000000. | | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
++++ | ++++ | ||
Line 1178: | Line 1402: | ||
| | |[8] |PRBSERR |RO |0x00 |This sticky status output indicates that PRBS errors have occurred. Value of error counter must be accessed via DRP. | | | | |[8] |PRBSERR |RO |0x00 |This sticky status output indicates that PRBS errors have occurred. Value of error counter must be accessed via DRP. | | ||
|::: |::: |[0] |PRBSLOCKED |RO |0x00 |Ignore this bit for GTX transceivers. For others: Indicates that the RX PRBS checker has been error free for 15 XCLK cycles after reset. Once asserted High, it does not deassert until reset of the RX pattern checker via PRBSCNTRESET | | |::: |::: |[0] |PRBSLOCKED |RO |0x00 |Ignore this bit for GTX transceivers. For others: Indicates that the RX PRBS checker has been error free for 15 XCLK cycles after reset. Once asserted High, it does not deassert until reset of the RX pattern checker via PRBSCNTRESET | | ||
- | ^Wed Feb 16 13:28:03 2022 ^^^^^^ | + | ^Tue Mar 14 10:17:59 2023 ^^^^^^ |
+ | ++++ | ||
+ | |||
+ | |||
+ | ==== PWM Generator (axi_pwm_gen) ==== | ||
+ | |||
+ | ++++ Click to expand regmap | | ||
+ | |< 100% 5% 5% 5% 25% 5% 5% 50% >| | ||
+ | |Address ||Bits |Name |Type |Default |Description | | ||
+ | |DWORD |BYTE |::: |::: |::: |::: |::: | | ||
+ | ^0x0000 ^0x0000 ^REG_VERSION ^^^^Version and Scratch Registers ^ | ||
+ | | | |[31:0] |VERSION[31: | ||
+ | ^0x0001 ^0x0004 ^REG_ID ^^^^Core ID ^ | ||
+ | | | |[31:0] |ID[31:0] |RO |0x00000000 |Instance identifier number. | | ||
+ | ^0x0002 ^0x0008 ^REG_SCRATCH ^^^^Version and Scratch Registers ^ | ||
+ | | | |[31:0] |SCRATCH[31: | ||
+ | ^0x0003 ^0x000c ^REG_CORE_MAGIC ^^^^Identification number ^ | ||
+ | | | |[31:0] |CORE_MAGIC[31: | ||
+ | ^0x0004 ^0x0010 ^REG_RSTN ^^^^Reset and load values ^ | ||
+ | | | |[1] |LOAD_CONFIG |WO |0x0 |Loads the new values written in the config registers. | | ||
+ | |::: |::: |[0] |RESET |RW |0x0 |Reset, default is (0x0). | | ||
+ | ^0x0005 ^0x0014 ^REG_NB_PULSES ^^^^Number of pulses ^ | ||
+ | | | |[31:0] |NB_PULSES |RO |0x0000 |Number of configurable pulses. | | ||
+ | ^0x0010 ^0x0040 ^REG_PULSE_X_PERIOD ^^^^Pulse x period ^ | ||
+ | | | |[31:0] |PULSE_X_PERIOD[31: | ||
+ | ^0x0020 ^0x0080 ^REG_PULSE_X_WIDTH ^^^^Pulse x width ^ | ||
+ | | | |[31:0] |PULSE_X_WIDTH[31: | ||
+ | ^0x0030 ^0x00C0 ^REG_PULSE_X_OFFSET ^^^^Pulse x offset ^ | ||
+ | | | |[31:0] |PULSE_X_OFFSET[31: | ||
++++ | ++++ | ||
~~NOTOC~~ | ~~NOTOC~~ | ||