This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
resources:fpga:docs:axi_tdd [12 Oct 2021 16:54] – Edit footer Iulia Moldovan | resources:fpga:docs:axi_tdd [27 Jul 2023 21:56] (current) – Removed obsolete linux references Ionut Podgoreanu | ||
---|---|---|---|
Line 1: | Line 1: | ||
- | ====== | + | ====== |
TDD (Time-Division Duplex) mode allows the user to control the time period of the receive and transmit bursts. | TDD (Time-Division Duplex) mode allows the user to control the time period of the receive and transmit bursts. | ||
- | The AXI TDD engine | + | The generic |
+ | |||
+ | The reason of creating | ||
===== Features ===== | ===== Features ===== | ||
- | * 6 independent output channels | + | * Up to 32 independent output channels |
- | * Primary | + | * Start/stop time values per channel |
- | * 24 bit accumulator | + | * Enable |
- | * External (1 PPS, shared or from GPSDO, etc.) synchronization | + | * 32 bit-max internal reference counter |
+ | * Initial startup delay before waveform generation | ||
+ | * Configurable frame length and number of frames per burst | ||
+ | * 3 sources of synchronization: external, internal and software generated | ||
- | ===== Utilization | + | ===== Files ===== |
- | ^ Device Family | + | ^ Name ^ Description |
- | | Xilinx Zynq UltraScale+ | + | | [[https:// |
+ | | [[https:// | ||
+ | | [[https:// | ||
+ | | [[https:// | ||
+ | | [[https:// | ||
+ | | [[https:// | ||
+ | | [[https:// | ||
+ | | [[https:// | ||
- | ===== Files ===== | + | ===== Synthesis Configuration Parameters |
- | ^ Name ^ Description ^ | + | ^ Name ^ Description |
- | | [[https:// | + | | '' |
- | | [[https:// | + | | '' |
- | | [[https:// | + | | '' |
- | | [[https:// | + | | '' |
- | | [[https:// | + | | '' |
+ | | '' | ||
+ | | '' | ||
+ | | '' | ||
+ | | '' | ||
+ | ===== Signal and Interface Pins ===== | ||
+ | {{: | ||
+ | ^ Name ^ Type ^ Description ^ | ||
+ | | '' | ||
+ | | '' | ||
+ | | '' | ||
+ | | '' | ||
+ | | '' | ||
+ | | '' | ||
+ | | '' | ||
+ | | '' | ||
+ | ===== Register Map ===== | ||
+ | |||
+ | {{page>: | ||
+ | |||
+ | |< 100% 10em 10em >| | ||
+ | ^ Access Type ^ Name ^ Description ^ | ||
+ | | R | Read-only | Reads will return the current register value. Writes have no effect. | | ||
+ | | RW | Read-write | Reads will return the current register value. Writes will change the current register value. | | ||
+ | | U | Unimplemented | Register field is unimplemented. | | ||
===== Theory of Operation ===== | ===== Theory of Operation ===== | ||
- | The central idea of the TDD engine | + | The central idea of the TDD controller |
{{: | {{: | ||
Line 43: | Line 79: | ||
==== Detailed description ==== | ==== Detailed description ==== | ||
- | When there is asymmetry (caused | + | In order to begin its operation, the peripheral must be enabled. This is done by setting |
- | There will be a fixed time offset between every i-th RX and TX sample, synchronizing | + | |
- | AXI TDD divides data streams into frames | + | The external synchronization capability allows the alignment of frames |
- | + | ||
- | The TDD control contains 2 counters: a 24 bit free running counter | + | |
- | + | ||
- | The frame counter counts to the length of the current frame that is processed, and marks further if the end of the frame has been reached (also resetting the counter). Depending | + | |
- | The end of a burst is marked by the last burst and the end of the frame. | + | |
- | + | ||
- | The frame counter | + | |
- | When counter is working (ON state), and either | + | |
- | When the counter is stopped (OFF state), it can be turned on again by enabling the TDD. | + | |
- | + | ||
- | + | ||
- | ==== I/O Interface ==== | + | |
- | + | ||
- | {{: | + | |
- | + | ||
- | ^ Interface ^ Pin ^ Type ^ Description ^ | + | |
- | | **Core clock and reset** |||| | + | |
- | | | '' | + | |
- | | | '' | + | |
- | | **TDD control interface** |||| | + | |
- | | | '' | + | |
- | | | '' | + | |
- | | | '' | + | |
- | | | '' | + | |
- | | | '' | + | |
- | | | '' | + | |
- | | | '' | + | |
- | | **TDD sync interface** |||| | + | |
- | | | '' | + | |
- | | | '' | + | |
- | | **AXI4 Lite interface** |||| | + | |
- | | | '' | + | |
- | + | ||
- | + | ||
- | ===== Register Map ===== | + | |
- | < | + | The next diagram shows the peripheral’s FSM, which transitions between 4 states: IDLE, ARMED, WAITING and RUNNING. |
- | |< 100% 5% 5% 5% 25% 5% 5% 50% >| | + | {{:resources:fpga:docs:axi_tdd:axi_tdd_fsm.png?500|}} |
- | |Address ||Bits |Name |Type |Default |Description | | + | |
- | |DWORD |BYTE |::: |::: |::: |::: |::: | | + | |
- | ^0x0010 ^0x0040 ^REG_TDD_CONTROL_0 ^^^^TDD Control & Status ^ | + | |
- | | | |[5] |TDD_GATED_TX_DMAPATH |RW |0x0 |If this bit is set, the core requests data from the TX DMA, just when the data path is active. Otherwise will requests continuously on the adjusted rate. The purpose of this feature is to facilitate debug. This bit must be SET to preserve data integrity. | | + | |
- | |::: |::: |[4] |TDD_GATED_RX_DMAPATH |RW |0x0 |If this bit is set, the core provides data for the RX DMA, just when the data path is active. Otherwise will provides continuously on the adjusted rate. The purpose of this feature is to facilitate debug. This bit must be SET to preserve data integrity. | | + | |
- | |::: |::: |[3] |TDD_TXONLY |RW |0x0 |If this bit is set- the TDD controller ignores all the TX_* timing registers | + | |
- | |::: |::: |[2] |TDD_RXONLY |RW |0x0 |If this bit is set- the TDD controller ignores all the RX_* timing registers | + | |
- | |::: |::: |[1] |TDD_SECONDARY |RW |0x0 |Enable the secondary transmit/ | + | |
- | |::: |::: |[0] |TDD_ENABLE |RW |0x0 |If set, enables the TDD controller- software must set this bit after programming | + | |
- | ^0x0011 ^0x0044 ^REG_TDD_CONTROL_1 ^^^^TDD Control & Status ^ | + | |
- | | | |[7:0] |TDD_BURST_COUNT |RW |0x00 |If set to 0x0 and enabled (TDD_ENABLE is set) - the controller operates in TDD mode as long as the TDD_ENABLE bit is set. If set to a non-zero value, the controller operates for the set number of frames and stops. | | + | |
- | ^0x0012 ^0x0048 ^REG_TDD_CONTROL_2 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_COUNTER_INIT |RW |0x000000 |The controller sets the frame counter to this value when starting TDD operation. | + | |
- | ^0x0013 ^0x004c ^REG_TDD_FRAME_LENGTH ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_FRAME_LENGTH |RW |0x000000 |The frame length is the terminal count for the 10ms counter running at the digital | + | |
- | ^0x0014 ^0x0050 ^REG_TDD_SYNC_TERMINAL_TYPE ^^^^TDD Control & Status ^ | + | |
- | | | |[0] |TDD_SYNC_TERMINAL_TYPE |RW |0x0 |Set this bit, if the current terminal will generate the syncronization pulse, reset otherwise. | | + | |
- | ^0x0018 ^0x0060 ^REG_TDD_STATUS ^^^^TDD Control & Status ^ | + | |
- | | | |[0] |TDD_RXTX_VCO_OVERLAP |RO |0x0 |This bit is asserted, if exist a time interval when both the TX and RX VCOs are powered up. | | + | |
- | |::: |::: |[1] |TDD_RXTX_RF_OVERLAP |RO |0x0 |This bit is asserted, if exist a time interval when both the TX and RX RF datapath are powered up. | | + | |
- | ^0x0020 ^0x0080 ^REG_TDD_VCO_RX_ON_1 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_VCO_RX_ON_1 |RW |0x000000 |Defines the offset (from frame count equal zero), when the RX VCO powers up at the first time. The controller enables the receive VCO, when the frame count reaches this value. | + | |
- | ^0x0021 ^0x0084 ^REG_TDD_VCO_RX_OFF_1 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_VCO_RX_OFF_1 |RW |0x000000 |Defines the offset (from frame count equal zero), when the RX VCO powers down at the first time. The controller disables the receive VCO, when the frame count reaches this value. | + | |
- | ^0x0022 ^0x0088 ^REG_TDD_VCO_TX_ON_1 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_VCO_TX_ON_1 |RW |0x000000 |Defines the offset (from frame count equal zero), when the TX VCO powers up at the first time. The controller enables the transmit VCO, when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid. | | + | |
- | ^0x0023 ^0x008c ^REG_TDD_VCO_TX_OFF_1 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_VCO_TX_OFF_1 |RW |0x000000 |Defines the offset (from frame count equal zero), when the TX VCO powers down at the first time. The controller disables the transmit VCO when the frame count reaches this value. | + | |
- | ^0x0024 ^0x0090 ^REG_TDD_RX_ON_1 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_RX_ON_1 |RW |0x000000 |Defines the offset (from frame count equal zero), when the RX data path is activated at the first time. The controller enables the receive chain when the frame count reaches this value. | + | |
- | ^0x0025 ^0x0094 ^REG_TDD_RX_OFF_1 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_RX_OFF_1 |RW |0x000000 |Defines the offset (from frame count equal zero), when the RX data path is deactivated the first time. The controller disables the receive chain when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid. | + | |
- | ^0x0026 ^0x0098 ^REG_TDD_TX_ON_1 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_TX_ON_1 |RW |0x000000 |Defines the offset (from frame count equal zero), when the TX data path is activated at the first time. The controller enables the transmit chain, when the frame count reaches this value. This register and the TX_DP_ON register controls the delay between the data path being activated and the time to actually push the transmit data through the transmit chain in the device. | | + | |
- | ^0x0027 ^0x009c ^REG_TDD_TX_OFF_1 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_TX_OFF_1 |RW |0x000000 |Defines the offset (from frame count equal zero), when the TX data path is deactivated at the first time. The controller disables the transmit chain, when the frame count reaches this value. This register and the TX_DP_OFF register controls the delay between the data path being deactivated and the time to actually stop transmitting data through the transmit chain in the device. | | + | |
- | ^0x0028 ^0x00a0 ^REG_TDD_RX_DP_ON_1 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_RX_DP_ON_1 |RW |0x000000 |Defines the offset (from frame count equal zero), when the controller starts to accept data from the digital interface for receive. | | + | |
- | ^0x0029 ^0x00a4 ^REG_TDD_RX_DP_OFF_1 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_RX_DP_OFF_1 |RW |0x000000 |Defines the offset (from frame count equal zero), when the controller stops to accept data from the digital interface for receive. | | + | |
- | ^0x002A ^0x00a8 ^REG_TDD_TX_DP_ON_1 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_TX_DP_ON_1 |RW |0x000000 |Defines the offset (from frame count equal zero), when the controller starts to request data from the system memory for transmit. The data rate is controlled by the TDD controller. | | + | |
- | ^0x002B ^0x00ac ^REG_TDD_TX_DP_OFF_1 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_TX_DP_OFF_1 |RW |0x000000 |Defines the offset (from frame count equal zero), when the controller stop requesting data from the system memory for transmit. | | + | |
- | ^0x0030 ^0x00c0 ^REG_TDD_VCO_RX_ON_2 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_VCO_RX_ON_2 |RW |0x000000 |The secondary pointer for VCO_RX_ON. | + | |
- | ^0x0031 ^0x00c4 ^REG_TDD_VCO_RX_OFF_2 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_VCO_RX_OFF_2 |RW |0x000000 |The secondary pointer for VCO_RX_OFF. | | + | |
- | ^0x0032 ^0x00c8 ^REG_TDD_VCO_TX_ON_2 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_VCO_TX_ON_2 |RW |0x000000 |The secondary pointer for VCO_TX_ON. | | + | |
- | ^0x0033 ^0x00cc ^REG_TDD_VCO_TX_OFF_2 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_VCO_TX_OFF_2 |RW |0x000000 |The secondary pointer for VCO_TX_OFF. | | + | |
- | ^0x0034 ^0x00d0 ^REG_TDD_RX_ON_2 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_RX_ON_2 |RW |0x000000 |The secondary pointer for RX_ON. | | + | |
- | ^0x0035 ^0x00d4 ^REG_TDD_RX_OFF_2 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_RX_OFF_2 |RW |0x000000 |The secondary pointer for RX_OFF. | | + | |
- | ^0x0036 ^0x00d8 ^REG_TDD_TX_ON_2 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_TX_ON_2 |RW |0x000000 |The secondary pointer for TX_ON. | | + | |
- | ^0x0037 ^0x00dc ^REG_TDD_TX_OFF_2 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_TX_OFF_2 |RW |0x000000 |The secondary pointer for TX_OFF. | | + | |
- | ^0x0038 ^0x00e0 ^REG_TDD_RX_DP_ON_2 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_RX_DP_ON_2 |RW |0x000000 |The secondary pointer for RX_DP_ON. | | + | |
- | ^0x0039 ^0x00e4 ^REG_TDD_RX_DP_OFF_2 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_RX_DP_OFF_2 |RW |0x000000 |The secondary pointer for RX_DP_OFF. | | + | |
- | ^0x003A ^0x00e8 ^REG_TDD_TX_DP_ON_2 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_TX_DP_ON_2 |RW |0x000000 |The secondary pointer for TX_DP_ON. | | + | |
- | ^0x003B ^0x00ec ^REG_TDD_TX_DP_OFF_2 ^^^^TDD Control & Status ^ | + | |
- | | | |[23:0] |TDD_TX_DP_OFF_2 |RW |0x000000 |The secondary pointer for TX_DP_OFF. | | + | |
- | </ | + | In case a synchronization signal is received while the TDD core is running, the signal can reset the internal counter to zero by setting '' |
+ | The generic TDD controller can have up to 32 output channels, each of them having its unique values when the channel is set/reset under '' | ||
- | ===== Linux IIO Driver ===== | + | Every bit in '' |
- | The [[https:// | + | The following registers will not be updated unless |
+ | * '' | ||
+ | * '' | ||
+ | * '' | ||
+ | * '' | ||
+ | * '' | ||
+ | * '' | ||
+ | * '' | ||
+ | * '' | ||
- | < | + | The user should configure them before enabling the peripheral. Any subsequent write while the peripheral is enabled will be ignored. |
- | axi_tdd_0: axi-tdd-0@9c460000 { | + | |
- | compatible = " | + | |
- | reg = < | + | |
- | clocks = <& | + | |
- | clock-names = " | + | |
- | }; | + | |
- | </ | + | |
- | <note tip> | + | An exception |
- | The driver needs to know which clock is driving the main clock input '' | + | |
- | </ | + | |
- | The resulting IIO device looks like this, where there is one channel per combination of '' | + | '' |
- | < | + | |
- | iio: | + | |
- | 4 channels found: | + | |
- | data1: | + | |
- | 6 channel-specific attributes found: | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | data1: | + | |
- | 6 channel-specific attributes found: | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | data0: | + | |
- | 6 channel-specific attributes found: | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | data0: | + | |
- | 6 channel-specific attributes found: | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | 10 device-specific attributes found: | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | attr | + | |
- | 1 debug attributes found: | + | |
- | debug attr 0: direct_reg_access value: 0x10061 | + | |
- | No trigger on this device | + | |
- | </ | + | |
- | | [[https:// | + | By adapting the synthesis parameters to the application requirements, |
{{navigation HDL User Guide# | {{navigation HDL User Guide# |