Address | Bits | Name | Type | Default | Description |
DWORD | BYTE |
0x0000 | 0x0000 | VERSION | Version of the peripheral. Follows semantic versioning. Current version 2.00.61. |
| | [31:16] | VERSION_MAJOR | R | 0x0002 | |
[15:8] | VERSION_MINOR | R | 0x00 | |
[7:0] | VERSION_PATCH | R | 0x61 | |
0x0001 | 0x0004 | PERIPHERAL_ID | |
| | [31:0] | PERIPHERAL_ID | R | ID | Value of the ID configuration parameter. |
0x0002 | 0x0008 | SCRATCH | |
| | [31:0] | SCRATCH | RW | 0x00000000 | Scratch register useful for debug. |
0x0003 | 0x000c | IDENTIFICATION | |
| | [31:0] | IDENTIFICATION | R | 0x5444444E | Peripheral identification ('T', 'D', 'D', 'N'). |
0x0004 | 0x0010 | INTERFACE_DESCRIPTION | |
| | [30:24] | SYNC_COUNT_WIDTH | R | SYNC_COUNT_WIDTH | Width of internal synchronization counter |
[21:16] | BURST_COUNT_WIDTH | R | BURST_COUNT_WIDTH | Width of burst counter |
[13:8] | REGISTER_WIDTH | R | REGISTER_WIDTH | Width of internal reference counter and timing registers |
[7] | SYNC_EXTERNAL_CDC | R | SYNC_EXTERNAL_CDC | Enable CDC for external synchronization pulse |
[6] | SYNC_EXTERNAL | R | SYNC_EXTERNAL | Enable external synchronization support |
[5] | SYNC_INTERNAL | R | SYNC_INTERNAL | Enable internal synchronization support |
[4:0] | CHANNEL_COUNT_EXTRA | R | CHANNEL_COUNT -1 | Number of channels starting from CH1, excluding CH0 |
0x0005 | 0x0014 | DEFAULT_POLARITY | |
| | [31:0] | DEFAULT_POLARITY | R | DEFAULT_POLARITY | Default polarity per every channel - LSB corresponds to CH0, MSB to CH31 |
0x0010 | 0x0040 | CONTROL | TDD Control |
| | [4] | SYNC_SOFT | RW | 0x0 | Trigger the TDD core through a register write. This bit self clears. |
[3] | SYNC_EXT | RW | 0x0 | Enable external sync trigger. This bit is implemented if SYNC_EXTERNAL is set. |
[2] | SYNC_INT | RW | 0x0 | Enable internal sync trigger. This bit is implemented if SYNC_INTERNAL is set. |
[1] | SYNC_RST | RW | 0x0 | Reset the internal counter while running when receiving a sync event |
[0] | ENABLE | RW | 0x0 | Module enable |
0x0011 | 0x0044 | CHANNEL_ENABLE | TDD Channel Enable |
| | [31:0] | CHANNEL_ENABLE | RW | 0x00000000 | Enable bits per channel - LSB corresponds to CH0, MSB to CH31 |
0x0012 | 0x0048 | CHANNEL_POLARITY | TDD Channel Polarity |
| | [31:0] | CHANNEL_POLARITY | RW | 0x00000000 | Polarity bits per channel - LSB corresponds to CH0, MSB to CH31 |
0x0013 | 0x004c | BURST_COUNT | TDD Number of frames per burst |
| | [31:0] | BURST_COUNT | RW | 0x00000000 | If set to 0x0 and enabled - the controller operates in TDD mode as long as the ENABLE bit is set. If set to a non-zero value, the controller operates for the set number of frames and then stops. |
0x0014 | 0x0050 | STARTUP_DELAY | TDD Transmission startup delay |
| | [31:0] | STARTUP_DELAY | RW | 0x00000000 | The initial delay value before the beginning of the first frame; defined in clock cycles. |
0x0015 | 0x0054 | FRAME_LENGTH | TDD Frame length |
| | [31:0] | FRAME_LENGTH | RW | 0x00000000 | The length of the transmission frame; defined in clock cycles. |
0x0016 | 0x0058 | SYNC_COUNTER_LOW | TDD Sync counter |
| | [31:0] | SYNC_COUNTER_LOW | RW | 0x00000000 | The LSB slice of the offset (from sync counter equal zero) when an internal sync pulse is generated. This register is implemented if SYNC_COUNT_WIDTH >0. |
0x0017 | 0x005c | SYNC_COUNTER_HIGH | TDD Sync counter |
| | [31:0] | SYNC_COUNTER_HIGH | RW | 0x00000000 | The MSB slice of the offset (from sync counter equal zero) when an internal sync pulse is generated. This register is implemented if SYNC_COUNT_WIDTH >32. |
0x0018 | 0x0060 | STATUS | Peripheral Status |
| | [1:0] | STATE | R | 0x0 | The current state of the peripheral FSM; used for debugging purposes. |
0x0020 | 0x0080 | CH0_ON | Channel Set |
| | [31:0] | CH0_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH0 is set. |
0x0021 | 0x0084 | CH0_OFF | Channel Reset |
| | [31:0] | CH0_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH0 is reset. |
0x0022 | 0x0088 | CH1_ON | Channel Set |
| | [31:0] | CH1_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH1 is set. This register is implemented if CHANNEL_COUNT >1. |
0x0023 | 0x008c | CH1_OFF | Channel Reset |
| | [31:0] | CH1_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH1 is reset. This register is implemented if CHANNEL_COUNT >1. |
0x0024 | 0x0090 | CH2_ON | Channel Set |
| | [31:0] | CH2_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH2 is set. This register is implemented if CHANNEL_COUNT >2. |
0x0025 | 0x0094 | CH2_OFF | Channel Reset |
| | [31:0] | CH2_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH2 is reset. This register is implemented if CHANNEL_COUNT >2. |
0x0026 | 0x0098 | CH3_ON | Channel Set |
| | [31:0] | CH3_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH3 is set. This register is implemented if CHANNEL_COUNT >3. |
0x0027 | 0x009c | CH3_OFF | Channel Reset |
| | [31:0] | CH3_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH3 is reset. This register is implemented if CHANNEL_COUNT >3. |
0x0028 | 0x00a0 | CH4_ON | Channel Set |
| | [31:0] | CH4_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH4 is set. This register is implemented if CHANNEL_COUNT >4. |
0x0029 | 0x00a4 | CH4_OFF | Channel Reset |
| | [31:0] | CH4_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH4 is reset. This register is implemented if CHANNEL_COUNT >4. |
0x002A | 0x00a8 | CH5_ON | Channel Set |
| | [31:0] | CH5_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH5 is set. This register is implemented if CHANNEL_COUNT >5. |
0x002B | 0x00ac | CH5_OFF | Channel Reset |
| | [31:0] | CH5_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH5 is reset. This register is implemented if CHANNEL_COUNT >5. |
0x002C | 0x00b0 | CH6_ON | Channel Set |
| | [31:0] | CH6_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH6 is set. This register is implemented if CHANNEL_COUNT >6. |
0x002D | 0x00b4 | CH6_OFF | Channel Reset |
| | [31:0] | CH6_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH6 is reset. This register is implemented if CHANNEL_COUNT >6. |
0x002E | 0x00b8 | CH7_ON | Channel Set |
| | [31:0] | CH7_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH7 is set. This register is implemented if CHANNEL_COUNT >7. |
0x002F | 0x00bc | CH7_OFF | Channel Reset |
| | [31:0] | CH7_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH7 is reset. This register is implemented if CHANNEL_COUNT >7. |
0x0030 | 0x00c0 | CH8_ON | Channel Set |
| | [31:0] | CH8_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH8 is set. This register is implemented if CHANNEL_COUNT >8. |
0x0031 | 0x00c4 | CH8_OFF | Channel Reset |
| | [31:0] | CH8_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH8 is reset. This register is implemented if CHANNEL_COUNT >8. |
0x0032 | 0x00c8 | CH9_ON | Channel Set |
| | [31:0] | CH9_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH9 is set. This register is implemented if CHANNEL_COUNT >9. |
0x0033 | 0x00cc | CH9_OFF | Channel Reset |
| | [31:0] | CH9_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH9 is reset. This register is implemented if CHANNEL_COUNT >9. |
0x0034 | 0x00d0 | CH10_ON | Channel Set |
| | [31:0] | CH10_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH10 is set. This register is implemented if CHANNEL_COUNT >10. |
0x0035 | 0x00d4 | CH10_OFF | Channel Reset |
| | [31:0] | CH10_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH10 is reset. This register is implemented if CHANNEL_COUNT >10. |
0x0036 | 0x00d8 | CH11_ON | Channel Set |
| | [31:0] | CH11_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH11 is set. This register is implemented if CHANNEL_COUNT >11. |
0x0037 | 0x00dc | CH11_OFF | Channel Reset |
| | [31:0] | CH11_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH11 is reset. This register is implemented if CHANNEL_COUNT >11. |
0x0038 | 0x00e0 | CH12_ON | Channel Set |
| | [31:0] | CH12_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH12 is set. This register is implemented if CHANNEL_COUNT >12. |
0x0039 | 0x00e4 | CH12_OFF | Channel Reset |
| | [31:0] | CH12_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH12 is reset. This register is implemented if CHANNEL_COUNT >12. |
0x003A | 0x00e8 | CH13_ON | Channel Set |
| | [31:0] | CH13_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH13 is set. This register is implemented if CHANNEL_COUNT >13. |
0x003B | 0x00ec | CH13_OFF | Channel Reset |
| | [31:0] | CH13_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH13 is reset. This register is implemented if CHANNEL_COUNT >13. |
0x003C | 0x00f0 | CH14_ON | Channel Set |
| | [31:0] | CH14_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH14 is set. This register is implemented if CHANNEL_COUNT >14. |
0x003D | 0x00f4 | CH14_OFF | Channel Reset |
| | [31:0] | CH14_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH14 is reset. This register is implemented if CHANNEL_COUNT >14. |
0x003E | 0x00f8 | CH15_ON | Channel Set |
| | [31:0] | CH15_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH15 is set. This register is implemented if CHANNEL_COUNT >15. |
0x003F | 0x00fc | CH15_OFF | Channel Reset |
| | [31:0] | CH15_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH15 is reset. This register is implemented if CHANNEL_COUNT >15. |
0x0040 | 0x0100 | CH16_ON | Channel Set |
| | [31:0] | CH16_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH16 is set. This register is implemented if CHANNEL_COUNT >16. |
0x0041 | 0x0104 | CH16_OFF | Channel Reset |
| | [31:0] | CH16_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH16 is reset. This register is implemented if CHANNEL_COUNT >16. |
0x0042 | 0x0108 | CH17_ON | Channel Set |
| | [31:0] | CH17_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH17 is set. This register is implemented if CHANNEL_COUNT >17. |
0x0043 | 0x010c | CH17_OFF | Channel Reset |
| | [31:0] | CH17_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH17 is reset. This register is implemented if CHANNEL_COUNT >17. |
0x0044 | 0x0110 | CH18_ON | Channel Set |
| | [31:0] | CH18_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH18 is set. This register is implemented if CHANNEL_COUNT >18. |
0x0045 | 0x0114 | CH18_OFF | Channel Reset |
| | [31:0] | CH18_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH18 is reset. This register is implemented if CHANNEL_COUNT >18. |
0x0046 | 0x0118 | CH19_ON | Channel Set |
| | [31:0] | CH19_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH19 is set. This register is implemented if CHANNEL_COUNT >19. |
0x0047 | 0x011c | CH19_OFF | Channel Reset |
| | [31:0] | CH19_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH19 is reset. This register is implemented if CHANNEL_COUNT >19. |
0x0048 | 0x0120 | CH20_ON | Channel Set |
| | [31:0] | CH20_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH20 is set. This register is implemented if CHANNEL_COUNT >20. |
0x0049 | 0x0124 | CH20_OFF | Channel Reset |
| | [31:0] | CH20_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH20 is reset. This register is implemented if CHANNEL_COUNT >20. |
0x004A | 0x0128 | CH21_ON | Channel Set |
| | [31:0] | CH21_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH21 is set. This register is implemented if CHANNEL_COUNT >21. |
0x004B | 0x012c | CH21_OFF | Channel Reset |
| | [31:0] | CH21_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH21 is reset. This register is implemented if CHANNEL_COUNT >21. |
0x004C | 0x0130 | CH22_ON | Channel Set |
| | [31:0] | CH22_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH22 is set. This register is implemented if CHANNEL_COUNT >22. |
0x004D | 0x0134 | CH22_OFF | Channel Reset |
| | [31:0] | CH22_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH22 is reset. This register is implemented if CHANNEL_COUNT >22. |
0x004E | 0x0138 | CH23_ON | Channel Set |
| | [31:0] | CH23_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH23 is set. This register is implemented if CHANNEL_COUNT >23. |
0x004F | 0x013c | CH23_OFF | Channel Reset |
| | [31:0] | CH23_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH23 is reset. This register is implemented if CHANNEL_COUNT >23. |
0x0050 | 0x0140 | CH24_ON | Channel Set |
| | [31:0] | CH24_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH24 is set. This register is implemented if CHANNEL_COUNT >24. |
0x0051 | 0x0144 | CH24_OFF | Channel Reset |
| | [31:0] | CH24_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH24 is reset. This register is implemented if CHANNEL_COUNT >24. |
0x0052 | 0x0148 | CH25_ON | Channel Set |
| | [31:0] | CH25_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH25 is set. This register is implemented if CHANNEL_COUNT >25. |
0x0053 | 0x014c | CH25_OFF | Channel Reset |
| | [31:0] | CH25_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH25 is reset. This register is implemented if CHANNEL_COUNT >25. |
0x0054 | 0x0150 | CH26_ON | Channel Set |
| | [31:0] | CH26_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH26 is set. This register is implemented if CHANNEL_COUNT >26. |
0x0055 | 0x0154 | CH26_OFF | Channel Reset |
| | [31:0] | CH26_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH26 is reset. This register is implemented if CHANNEL_COUNT >26. |
0x0056 | 0x0158 | CH27_ON | Channel Set |
| | [31:0] | CH27_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH27 is set. This register is implemented if CHANNEL_COUNT >27. |
0x0057 | 0x015c | CH27_OFF | Channel Reset |
| | [31:0] | CH27_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH27 is reset. This register is implemented if CHANNEL_COUNT >27. |
0x0058 | 0x0160 | CH28_ON | Channel Set |
| | [31:0] | CH28_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH28 is set. This register is implemented if CHANNEL_COUNT >28. |
0x0059 | 0x0164 | CH28_OFF | Channel Reset |
| | [31:0] | CH28_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH28 is reset. This register is implemented if CHANNEL_COUNT >28. |
0x005A | 0x0168 | CH29_ON | Channel Set |
| | [31:0] | CH29_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH29 is set. This register is implemented if CHANNEL_COUNT >29. |
0x005B | 0x016c | CH29_OFF | Channel Reset |
| | [31:0] | CH29_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH29 is reset. This register is implemented if CHANNEL_COUNT >29. |
0x005C | 0x0170 | CH30_ON | Channel Set |
| | [31:0] | CH30_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH30 is set. This register is implemented if CHANNEL_COUNT >30. |
0x005D | 0x0174 | CH30_OFF | Channel Reset |
| | [31:0] | CH30_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH30 is reset. This register is implemented if CHANNEL_COUNT >30. |
0x005E | 0x0178 | CH31_ON | Channel Set |
| | [31:0] | CH31_ON | RW | 0x00000000 | The offset (from frame count equal zero), when CH31 is set. This register is implemented if CHANNEL_COUNT >31. |
0x005F | 0x017c | CH31_OFF | Channel Reset |
| | [31:0] | CH31_OFF | RW | 0x00000000 | The offset (from frame count equal zero), when CH31 is reset. This register is implemented if CHANNEL_COUNT >31. |
Tue Mar 14 10:17:59 2023 | |