Wiki

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision Both sides next revision
resources:fpga:docs:axi_tdd [11 Oct 2021 15:12]
Iulia Moldovan Add footer
resources:fpga:docs:axi_tdd [12 Oct 2021 16:54]
Iulia Moldovan Edit footer
Line 1: Line 1:
-====== Timing-Division Duplexing ​(TDD) Controller ======+====== Timing-Division Duplexing Controller ======
  
-TDD (Time Division Duplex) mode allows the user to control the time period of the receive and transmit bursts. ​+TDD (Time-Division Duplex) mode allows the user to control the time period of the receive and transmit bursts. ​
  
 The AXI TDD engine is a relatively simple peripheral originally intended to be used for TDD (wireless) communication systems. It solves the synchronization issue when transmitting and receiving multiple frames of data through multiple buffers. The AXI TDD engine is a relatively simple peripheral originally intended to be used for TDD (wireless) communication systems. It solves the synchronization issue when transmitting and receiving multiple frames of data through multiple buffers.
Line 12: Line 12:
   * 24 bit accumulator   * 24 bit accumulator
   * External (1 PPS, shared or from GPSDO, etc.) synchronization to work with multiple devices   * External (1 PPS, shared or from GPSDO, etc.) synchronization to work with multiple devices
 +
  
 ===== Utilization ===== ===== Utilization =====
Line 27: Line 28:
 | [[https://​github.com/​analogdevicesinc/​linux/​blob/​master/​drivers/​iio/​adc/​cf_axi_tdd.c|cf_axi_tdd.c]] | TDD Linux Driver | | [[https://​github.com/​analogdevicesinc/​linux/​blob/​master/​drivers/​iio/​adc/​cf_axi_tdd.c|cf_axi_tdd.c]] | TDD Linux Driver |
 | [[https://​github.com/​analogdevicesinc/​linux/​blob/​master/​arch/​arm64/​boot/​dts/​xilinx/​zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts|zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts]] | Device tree using TDD | | [[https://​github.com/​analogdevicesinc/​linux/​blob/​master/​arch/​arm64/​boot/​dts/​xilinx/​zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts|zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts]] | Device tree using TDD |
 +
  
 ===== Theory of Operation ===== ===== Theory of Operation =====
Line 37: Line 39:
  
 <note tip>​While the above graphic shows all channels being enabled in a stacked manner, they are completely independent of each other!</​note>​ <note tip>​While the above graphic shows all channels being enabled in a stacked manner, they are completely independent of each other!</​note>​
 +
  
 ==== Detailed description ==== ==== Detailed description ====
Line 76: Line 79:
 | **AXI4 Lite interface** |||| | **AXI4 Lite interface** ||||
 |              | ''​s_axi_*''​ || Standard AXI Slave Memory Map interface | |              | ''​s_axi_*''​ || Standard AXI Slave Memory Map interface |
 +
  
 ===== Register Map ===== ===== Register Map =====
Line 152: Line 156:
  
 </​hidden>​ </​hidden>​
 +
  
 ===== Linux IIO Driver ===== ===== Linux IIO Driver =====
Line 225: Line 230:
  
  
-{{navigation #axi_ip|AXI IP#hdl|Main page#​tips|Using and modifying the HDL design}}+{{navigation ​HDL User Guide#ip_cores|IP cores#hdl|Main page#​tips|Using and modifying the HDL design}}
resources/fpga/docs/axi_tdd.txt · Last modified: 07 Oct 2022 06:48 by Ionut Podgoreanu