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resources:fpga:docs:axi_tdd [11 Oct 2021 15:12] – Add footer Iulia Moldovanresources:fpga:docs:axi_tdd [12 Oct 2021 16:54] – Edit footer Iulia Moldovan
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-====== Timing-Division Duplexing (TDD) Controller ======+====== Timing-Division Duplexing Controller ======
  
-TDD (Time Division Duplex) mode allows the user to control the time period of the receive and transmit bursts. +TDD (Time-Division Duplex) mode allows the user to control the time period of the receive and transmit bursts. 
  
 The AXI TDD engine is a relatively simple peripheral originally intended to be used for TDD (wireless) communication systems. It solves the synchronization issue when transmitting and receiving multiple frames of data through multiple buffers. The AXI TDD engine is a relatively simple peripheral originally intended to be used for TDD (wireless) communication systems. It solves the synchronization issue when transmitting and receiving multiple frames of data through multiple buffers.
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   * 24 bit accumulator   * 24 bit accumulator
   * External (1 PPS, shared or from GPSDO, etc.) synchronization to work with multiple devices   * External (1 PPS, shared or from GPSDO, etc.) synchronization to work with multiple devices
 +
  
 ===== Utilization ===== ===== Utilization =====
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 | [[https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/cf_axi_tdd.c|cf_axi_tdd.c]] | TDD Linux Driver | | [[https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/cf_axi_tdd.c|cf_axi_tdd.c]] | TDD Linux Driver |
 | [[https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts|zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts]] | Device tree using TDD | | [[https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts|zynqmp-zcu102-rev10-ad9081-m8-l4-tdd.dts]] | Device tree using TDD |
 +
  
 ===== Theory of Operation ===== ===== Theory of Operation =====
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 <note tip>While the above graphic shows all channels being enabled in a stacked manner, they are completely independent of each other!</note> <note tip>While the above graphic shows all channels being enabled in a stacked manner, they are completely independent of each other!</note>
 +
  
 ==== Detailed description ==== ==== Detailed description ====
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 | **AXI4 Lite interface** |||| | **AXI4 Lite interface** ||||
 |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface | |              | ''s_axi_*'' || Standard AXI Slave Memory Map interface |
 +
  
 ===== Register Map ===== ===== Register Map =====
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 </hidden> </hidden>
 +
  
 ===== Linux IIO Driver ===== ===== Linux IIO Driver =====
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-{{navigation #axi_ip|AXI IP#hdl|Main page#tips|Using and modifying the HDL design}}+{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/axi_tdd.txt · Last modified: 27 Jul 2023 21:56 by Ionut Podgoreanu

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