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resources:fpga:docs:axi_pwm_gen [11 Oct 2021 15:12] – Edit next page to be Using and modifying the HDL design Iulia Moldovanresources:fpga:docs:axi_pwm_gen [13 Oct 2021 10:07] – Edit footer & title Iulia Moldovan
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-====== axi_pwm_gen ======+====== AXI_PWM_GEN ======
  
 The axi_pwm_gen core is used to generate a maximum of four configurable signals(pwms). The pulses are generated according to the state of a counter, one counter for each pulse. The axi_pwm_gen core is used to generate a maximum of four configurable signals(pwms). The pulses are generated according to the state of a counter, one counter for each pulse.
  
-Features:+ 
 +===== Features ===== 
   - up to four configurable signals(period, width, offset)   - up to four configurable signals(period, width, offset)
   - external synchronization   - external synchronization
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 The axi_pwm_gen core can be synchronized by an external signal. The offset counter will wait for a high to low transition of the synchronization pulse. If another synchronization is needed, the external_sync signal should be set high and the load_config should be toggled(by register write). This will cause the counters to wait for another external_sync high to low transition. The axi_pwm_gen core can be synchronized by an external signal. The offset counter will wait for a high to low transition of the synchronization pulse. If another synchronization is needed, the external_sync signal should be set high and the load_config should be toggled(by register write). This will cause the counters to wait for another external_sync high to low transition.
 To disable a pwm, write 0 to it's period register. To disable a pwm, write 0 to it's period register.
 +
 +
 +===== Block Diagram =====
  
 {{ :resources:fpga:docs:axi_pwm_gen.png |}} {{ :resources:fpga:docs:axi_pwm_gen.png |}}
  
-==== Configuration Parameter ====+ 
 +===== Configuration Parameters =====
  
 ^ Name ^ Description ^ Default Value^ ^ Name ^ Description ^ Default Value^
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 | ''PULSE_3_OFFSET'' | Pulse 3 period (number of clk cycles) | 0 | | ''PULSE_3_OFFSET'' | Pulse 3 period (number of clk cycles) | 0 |
  
-==== Signal and Interface Pins ====+ 
 +===== Signal and Interface Pins =====
  
 ^ Interface ^ Pin ^ Type ^ Description ^ ^ Interface ^ Pin ^ Type ^ Description ^
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 {{ :resources:fpga:docs:pwm_gen_load_config.png?nolink |}} {{ :resources:fpga:docs:pwm_gen_load_config.png?nolink |}}
 +
  
 ===== Register map ===== ===== Register map =====
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 ^Tue Mar 30 10:21:25 2021 ^^^^^^ ^Tue Mar 30 10:21:25 2021 ^^^^^^
  
- +{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
-{{navigation #axi_ip|AXI IP#hdl|Main page#tips|Using and modifying the HDL design}}+
resources/fpga/docs/axi_pwm_gen.txt · Last modified: 18 Jan 2024 13:26 by Alin-Tudor Sferle

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