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The AXI_LOGIC_ANALYZER IP implements both an logic analyzer and a pattern generator, sharing the same pins
Interface | Pin | Type | Description |
---|---|---|---|
Clock Input | |||
clk | input | Main clock | |
Clock Output | |||
clk_out | output | Clock on which the logic analyzer / pattern generator related modules are running. It is a selection between clk and data[0] | |
Digital pins | |||
data_i | input[15:0] | Data input, used when working as logic analyzer | |
data_o | output[15:0] | Data output, used when working as pattern generator | |
data_t | output[15:0] | Data selection, switch between logic analyzer and pattern generator | |
trigger_i | input[1:0] | Trigger pins, controlled by another IP | |
Logic analyzer path | |||
adc_data | output[15:0] | Data for the logic analyzer path | |
adc_valid | input | Valid for the logic analyzer path | |
Pattern generator path | |||
dac_valid | input | Valid for the pattern generator path | |
dac_read | output | Read for the pattern generator path | |
dac_data | input[15:0] | Data for the pattern generator path | |
Trigger | |||
trigger_out | output | Triggers data acquisition on the logic analyzer DMAC | |
trigger_offset | output[31:0] | Controls the depth of the variable FIFO, used for history on the logic analyzer path | |
AXI_S_MM interface | |||
s_axi_* | Standard AXI Slave Memory Map interface |
The AXI_LOGIC_ANALYZER IP implements both a logic analyzer and a pattern generator functionality. There are 16-channel digital I/O pins. All the pins can be configured either as inputs (logic analyzer) or outputs (pattern generator). The pattern generator supports open drain outputs, configurable per pin. The logic analyzer path can work at lower than the maximum rate by configuring the down sampling block. The same thing is done for the pattern generator using the up sampling block. Triggering for the logic analyzer is implemented in this IP also. It can generate triggers based on ext trigger signals and the 16 bit input signals. In order to provide data before triggering, a variable length FIFO should be used with this IP. The length of the FIFO is configured through the TRIGGER_DELAY register. It can be bypassed if TRIGGER_DELAY is 0. For each of the 18 pins triggering can be done based on rise edge, fall edge, any edge, high or low.
Address | Bits | Name | Type | Description | |
DWORD | BYTE | ||||
0x0000 | 0x0000 | REG_VERSION | Version Register | ||
---|---|---|---|---|---|
[31:0] | VERSION | RO | Version number | ||
0x0001 | 0x0004 | REG_SCRATCH | Scratch Register | ||
[31:0] | SCRATCH | RW | Scratch register | ||
0x0002 | 0x0008 | REG_DIVIDER_COUNTER_LA | Downsampling Counter | ||
[31:0] | DIVIDER_COUNTER | RW | Register used for down sampling the logic analyzer data. Sample data every (divider_counter + 1) samples | ||
0x0003 | 0x000c | REG_DIVIDER_COUNTER_PG | Upsampling Counter | ||
[31:0] | DIVIDER_COUNTER | RW | Register used for upsampling pattern generator data. Sample data every (divider counter + 1) samples | ||
0x0004 | 0x0010 | REG_IO_SELECTION | Data Pins Direction | ||
[15:0] | DIRECTION | RW | Selects which pins are inputs(1) and which are outputs (0). Each bit configures the corresponding pin | ||
0x0005 | 0x0014 | REG_EDGE_DETECT_CONTROL | Any Edge Triggering | ||
[17:16] | TRIGGER[1:0] | RW | Enables any edge detection triggering based on the trigger pins | ||
[15:0] | DATA | RW | Enables any edge detection triggering based on the data pins | ||
0x0006 | 0x0018 | REG_RISE_EDGE_CONTROL | Rise Edge Triggering | ||
[17:16] | TRIGGER[1:0] | RW | Enables rise edge detection triggering based on the trigger pins | ||
[15:0] | DATA[15:0] | RW | Enables rise edge detection triggering based on the data pins | ||
0x0007 | 0x001c | REG_FALL_EDGE_CONTROL | Fall Edge Triggering | ||
[17:16] | TRIGGER[1:0] | RW | Enables fall edge detection triggering based on the trigger pins | ||
[15:0] | DATA[15:0] | RW | Enables fall edge detection triggering based on the data pins | ||
0x0008 | 0x0020 | REG_LOW_LEVEL_CONTROL | Low Level Triggering | ||
[17:16] | TRIGGER[1:0] | RW | Enables low level triggering based on the trigger pins | ||
[15:0] | DATA[15:0] | RW | Enables low level triggering based on the data pins | ||
0x0009 | 0x0024 | REG_HIGH_LEVEL_CONTROL | High Level Triggering | ||
[17:16] | TRIGGER[1:0] | RW | Enables high level triggering based on the trigger pins | ||
[15:0] | DATA[15:0] | RW | Enables high level triggering based on the data pins | ||
0x000A | 0x0028 | REG_TRIGGER_DELAY | Depth of the Trigger History FIFO | ||
[31:0] | TRIGGER_DELAY | RW | Controls the depth of the history FIFO. If set to 0, the FIFO is bypassed and reset | ||
0x000B | 0x002c | REG_TRIGGER_LOGIC | Trigger Mix | ||
[0] | TRIGGER_LOGIC | RW | Combines the enable triggers through an OR (0) or an AND (1) gate | ||
0x000C | 0x0030 | REG_CLOCK_SELECT | Clock Selection Multiplexer | ||
[0] | CLOCK_SELECT | RW | Selects between clk(0) and data[0] (1) as clock for the logic analyzer and pattern generator paths | ||
0x000D | 0x0034 | REG_OVERWRITE_MASK | Overwrite data_o Value | ||
[15:0] | OVERWRITE_MASK | RW | If set to 1, the specific data_o pin will be driven by the value written in the REG_OVERWRITE_DATA register, instead of the DMA | ||
0x000E | 0x0038 | REG_OVERWRITE_DATA | Overwrite Value For data_o | ||
[15:0] | OVERWRITE_DATA | RW | Overwrite value to drive data_o directly, when the mask is applied | ||
0x000F | 0x003c | REG_INPUT_DATA | Read the values on data_i bus | ||
[15:0] | INPUT_DATA | RO | The value of the input data, synchronized | ||
0x0010 | 0x0040 | REG_OUTPUT_MODE | Controls output type | ||
[0] | OUTPUT_MODE | RW | Data output is in push-pull (0) or open-drain(1) mode |