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resources:fpga:docs:axi_fan_control [11 Oct 2021 15:10] – Add footer Iulia Moldovanresources:fpga:docs:axi_fan_control [12 Oct 2021 16:50] (current) – Edit title & cosmetic changes Iulia Moldovan
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-      +====== AXI Fan Control IP Core ====== 
-====== Fan Control IP Core ====== + 
-The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_fan_control|axi_fan_control]] IP core is a software programmable fan controller. +The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_fan_control|axi_fan_control]] IP core is a software programmable fan controller. \\ 
-==== Block Diagram ====+Its purpose is to control the fan used for the cooling of a Xilinx Zynq Ultrascale+ MPSoC without the need of any external temperature sensors. \\ 
 +To achieve this, the IP core uses the PL SYSMONE4 primitive to obtain the PL temperature via the DRP interface. Based on the temperature readings it then outputs a PWM signal to control the fan rotation accordingly. The tacho signal coming from the fan is also measured and evaluated to ensure that the RPM is correct and the fan is working properly. 
 + 
 + 
 +===== Block Diagram ===== 
 {{:resources:fpga:docs:axi_fan_control_1.svg| AXI Fan Control block diagram}} {{:resources:fpga:docs:axi_fan_control_1.svg| AXI Fan Control block diagram}}
-  
  
-====== Introduction ====== 
-The purpose of this IP core is to control the fan used for the cooling of a Xilinx Zynq Ultrascale+ MPSoC without the need of any external temperature sensors. To achieve this, the IP core uses the PL SYSMONE4 primitive to obtain the PL temperature via the DRP interface. Based on the temperature readings it then outputs a PWM signal to control the fan rotation accordingly. The tacho signal coming from the fan is also measured and evaluated to ensure that the RPM is correct and the fan is working properly. 
  
 +===== Configuration Parameters =====
  
-==== Configuration Parameter ==== 
 ^ Name ^ Description ^ Default Value^ ^ Name ^ Description ^ Default Value^
 | ''PWM_FREQUENCY_HZ'' | Frequency of the PWM signal | 5000 [Hz] | | ''PWM_FREQUENCY_HZ'' | Frequency of the PWM signal | 5000 [Hz] |
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-==== Signal and Interface Pins ====+===== Signal and Interface Pins ===== 
 ^ Interface ^ Pin ^ Type ^ Description ^ ^ Interface ^ Pin ^ Type ^ Description ^
 |              | ''tacho'' | ''input'' | Tacho generator input | |              | ''tacho'' | ''input'' | Tacho generator input |
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-==== Register Map ====         +===== Clocking =====
-{{page>:resources:fpga:docs:hdl:regmap##Fan Controller (axi_fan_control)&nofooter&noeditbtn}} +
  
-==== Clocking ==== 
 The IP core runs on the AXI clock and requires a frequency of 100MHz. The IP core runs on the AXI clock and requires a frequency of 100MHz.
  
  
-==== Theory of Operation ====+===== Theory of Operation ===== 
 The main features of this IP core are its independent operation and the fact that it does not require an external temperature sensor. All of the mechanisms contained inside the core are controlled by a state machine, so that they do not depend on the software in case the software fails. The state machine uses the temperature it reads from the SYSMONE4 primitive or via the "temp_in" bus to decide the correct PWM duty-cycle. The temperature thresholds and hysteresis have defaults set in hardware and can be modified by the software. The INTERNAL_SYSMONE paramater is used to set the temperature values source, 0 when reading from temp_in and 1 when instantiating the internal SYSMONE primitive. The main features of this IP core are its independent operation and the fact that it does not require an external temperature sensor. All of the mechanisms contained inside the core are controlled by a state machine, so that they do not depend on the software in case the software fails. The state machine uses the temperature it reads from the SYSMONE4 primitive or via the "temp_in" bus to decide the correct PWM duty-cycle. The temperature thresholds and hysteresis have defaults set in hardware and can be modified by the software. The INTERNAL_SYSMONE paramater is used to set the temperature values source, 0 when reading from temp_in and 1 when instantiating the internal SYSMONE primitive.
  
  
-=== Running independently ===+==== Running independently ====
 The hardware can operate with no input from the software; the IP core starts working after the bitstream is loaded, without the need to be brought out of reset. In order to activate the interrupts the software must write to the IRQ_MASK register. At this point the hardware starts operating and a minimal feedback is provided. The hardware can operate with no input from the software; the IP core starts working after the bitstream is loaded, without the need to be brought out of reset. In order to activate the interrupts the software must write to the IRQ_MASK register. At this point the hardware starts operating and a minimal feedback is provided.
  
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-=== Software control and customization ===+==== Software control and customization ==== 
 The software can overwrite the temperature thresholds and the tacho values if needed. The TEMP_00_H -> TEMP_100_L registers can redefine the temperature intervals and the TACHO_25 -> TACHO_100 registers can also be used to redefine tacho values if a different fan is installed. In this case the TACHO_*_TOL registers must also be written in orded to provide tolerances. They must be calculated by the software as % of the nominal value //(i.e. 20% of 10000 = 2000)//.  The software can overwrite the temperature thresholds and the tacho values if needed. The TEMP_00_H -> TEMP_100_L registers can redefine the temperature intervals and the TACHO_25 -> TACHO_100 registers can also be used to redefine tacho values if a different fan is installed. In this case the TACHO_*_TOL registers must also be written in orded to provide tolerances. They must be calculated by the software as % of the nominal value //(i.e. 20% of 10000 = 2000)//. 
  
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-=== Interrupts ===+==== Interrupts ==== 
 The fan controller supports interrupts to both inform the software of any possible errors and also to facilitate the control of the core. There are four interrupt sources: The fan controller supports interrupts to both inform the software of any possible errors and also to facilitate the control of the core. There are four interrupt sources:
   *The ''PWM_CHANGED'' interrupt is generated at the end of the 5 second delay after a PWM duty-cycle change request. The request can come either from the software or from the hardware   *The ''PWM_CHANGED'' interrupt is generated at the end of the 5 second delay after a PWM duty-cycle change request. The request can come either from the software or from the hardware
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-{{navigation #axi_ip|AXI IP#hdl|Main page#tips|Using and modifying the HDL design}}+===== Register Map =====    
 +      
 +{{page>:resources:fpga:docs:hdl:regmap##Fan Controller (axi_fan_control)&nofooter&noeditbtn}} 
 + 
 +{{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}}
resources/fpga/docs/axi_fan_control.txt · Last modified: 12 Oct 2021 16:50 by Iulia Moldovan

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